An address register refers to a specific part of the memory of the computer which is used to store and keep track of the locations of data stored in the system memory.

From a technical perspective, it is a part of the Von Neumann architecture or a circuit that has high operating efficiency and speed to hold addresses of data to be handled or instructions to be completed.

These registers were created by a mathematician, John von Neumann following the principles of mathematics. He considered data to be a vector consisting of the following:

• A direction
• A magnitude

The registers he created stored both the data and the location of the data, which is also referred to as the path of the data.

Based on the above facts, the first two registers created by him were referred to as the following:

• The Memory Address Register, usually abbreviated as MAR.
• The Memory Data Register, usually abbreviated as MDR.

Typically, the MAR is used to store the locations or directions, and the MDR stores the data itself or the magnitude.

These stay in the respective registers until the data or vector and the instructions assigned for it are carried out.

However, this is not the official explanation of an address register.

In the world of computers, the Memory Address Register signifies the CPU register. These registers typically hold the following:

• The locations on the memory from where data will be fetched by the CPU registers
• The data addresses which will be sent through the system bus

This means, in other words, the address registers are used to hold and access data and instructions in and from the memory during the instruction execution phase.

The working process of the address registers differs according to the instruction types. For example:

• While reading data from the memory, the data addresses in the MAR are fed to the MDR first. It is then used by the CPU.
• While writing data to the memory, the reverse happens, where the CPU writes the data from the MDR to the memory location, and these addresses are stored in the MAR.

The MAR, which is located inside the CPU, usually goes to any of the following:

Usually, the MAR and the MDR are the two halves of the minimal interface between the computer storage and a microprogram.

However, in general, the MAR is also referred to as the parallel load register, since it holds the subsequent memory addresses that are to be manipulated, for example, the following address to be written or read.

The Memory Address Register can be further categorized into two unique groups such as:

• The Destination Memory Address Register or DMAR.
• The Source Memory Address Register or SMAR.

There are also two other types of memory address registers that are specially designed for operation control, such as:

• The Control Memory Address Register – This specific type of address register stipulates the addresses of the micro-instructions.
• The Control Data Register – This register stores the micro-instructions that are read from the memory.

Well, a micro-instruction comprises a control word. This word lays down one or a couple of micro-operations to be performed by the data processor.

Subsequent micro-instructions are searched from different locations, which may be located in different places, such as:

• The next one in the sequence
• Someplace else in the control memory

That is why it is recommended to use a few bits of the current micro-instruction for the next in order to have much better and more effective control over the generation of the addresses of all subsequent micro-instructions.

When these operations are accomplished, the controller then determines the succeeding address, which may be the function of the outward input condition as well.

## What Does an Address Register Do?

Just as the name implies, the address registers are designed to hold the addresses that are transferred to the memory unit.

In simple words, it acts as the storage space for memory units to be used to transfer data to the CPU for immediate use during data processing.

This transfer and storage of addresses can be handled typically in two specific ways such as:

• By following a bus approach
• By using a direct input statement for the memory

This means that the address registers, which are also referred to as the memory registers, basically form a part of the computer processor and typically perform as the processor register.

The Memory Address Register performs two specific functions such as:

• It stores the addresses of the present instructions needed to be fetched from the memory.
• It stores the address in memory where the data is to be moved.

When it uses the bus setting of the memory, it acts as a simple register. It sets the output to the value of the target address from the PC or IR when the control signal such as mar_load is high.

In a simple microprocessor, the MAR requires a sufficient number of bits for the location address. For example, the register size has to be 8 bits wide if the address itself needs that many bits.

The Memory Address Register, having a similar interface to the internal bus of the processor (mar_bus), which is demarcated as a typical logic direction in-out, typically sends two types of signals such as:

• Clock signals
• Reset signals

However, during the operation, only the initial 8 bits are used.

## What is a Base Address Register?

The Base Address Register (BAR) is actually a pointer to the byte in the memory. The number of bytes is specified by the offset.

In simple words, it means that the base address register helps in calculating the address with the help of a 12-bit offset, which is encoded within the instruction.

Usually, the Base Address Register is the record of the device address beginning at the memory.

This register is usually used for two specific purposes, such as:

• To specify the amount of memory required by a device to map it into the main memory
• To hold the base address after enumeration of the devices where the block of mapped memory starts

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There can be as many as six BARs of 32 bits in a device. However, two BARs can also be combined to form a 64-bit BAR. These BARs are usually at the endpoints and each of these endpoints can map a maximum of six memory regions.

You may wonder why you need two BARs when data is received or transferred by the Peripheral Component Interconnect Express (PCIe) and is stored in the memory location that is stated in the Base Address Register.

Well, you need two BARs of 64 bits for several good reasons such as:

• It will allow mapping a device larger than the 4 GB limit.
• One can be used as a configuration BAR and the other as a data exchange BAR.
• One can be used for input and the other for output.

The BAR maps the memory regions that are within the PCIe device so that after the mapping process is completed, the driver or the software can read or write to the storage of the device with the help of the mapped memory regions.

In such a situation, the memory access is directed to the device and not to the main memory of the system by the following:

• The memory controller inside the CPU
• The PCIe Root Complex
• The PCIe device tree

## What is an Address Register in DMA?

It actually refers to the start address in the Direct Memory Access (DMA) destination register where the data is to be copied.

This is usually a contiguous block, but the DMA source register can store the data address either in a contiguous block or in a scatter-gather list.

There is a DMA address register in every DMA channel which is responsible for holding the address of the initial memory location. This is what the DMA channel will access.

This means that in the DMA address register, the opening address of the block of the memory is first loaded in it and is accessed by the device, quite naturally.

Things are usually worked in the following way:

• The DMA registers are programmed first by the software running on the CPU. This will initiate the transfer of data through the DMA channel while the CPU can continue doing other tasks.
• The DMA controller or DMA engine will start reading the memory from the Source Start address. It will also write to the Destination Address.
• When a data transfer process is completed and before the next data transmission process starts, the DMA controller will ensure that the Source Start Address and the Destination Address both are updated.

The above steps are repeated until the Size Field that is programmed is reached. When it does so, an interrupt is triggered back to the CPU and an indication about the completion of the process is sent to the status registers.

## What is the Size of Address Register?

Typically, the size of the address register can range anywhere from 12 bits to 64 bits, depending on its type and the size of the memory.

In fact, it is the fact that the size of the address memory is related to the size of the memory that makes things a bit confusing and therefore needs further explanation and a closer look.

Historically, processors supported a wide and varied range of word sizes, measured in bits, which included the following:

• 8 bits
• 9 bits
• 10 bits
• 12 bits
• 18 bits
• 24 bits
• 36 bits
• 39 bits
• 40 bits
• 48 bits
• 60 bits

However, all the modern processors, even the embedded systems, do not support such a wide range of word sizes. Typically, they support only a few word sizes, such as:

• 8 bits
• 16 bits
• 24 bits
• 32 bits
• 64 bits

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And, as for the modern general-purpose computers they typically use 32 bits or 64 bits.

Another point to be noted at this point is that, more often than not, while the word size of a modern computer system is referred to, the size of the address space on that specific computer is also described along with it.

Therefore, when you say that a computer is “32-bit,” you also refer to the fact that it supports memory addresses which are 32 bits in size as well.

So, mathematically, if a 32-bit computer is byte-addressable, it can address as many as 232 bytes of memory, which is equal to 4,294,967,296 bytes or 4 gibibytes (GiB).

With such a size, a single memory address can be stored effectively in one word.

However, this is not the case always and every time, given the fact that the memory addresses in a computer can be both larger or smaller than their word size.

For example:

• Several 8-bit processors, such as the MOS Technology 6502, support 16-bit addresses which allows them to cross the limit of a measly 256 bytes of memory addressing.
• The 16-bit processors, such as the Intel 8088 and Intel 8086, support 20-bit addressing with the help of segmentation, which allows them to access 1 MiB of memory in place of just 64 KiB.
• All of the Intel Pentium processors launched after the Pentium Pro come with Physical Address Extensions or PAE to support mapping physical addresses of 36 bits to virtual addresses of 32 bits.
• Several processors, such as the 36-bit CPUs of the earlier days used to store two addresses in each word.

Based on simple theory and math, the byte-addressable 64-bit modern computer systems can address 264 bytes or 16 exbibytes. However, the amount of memory in practice is limited by different factors, which include but are not limited to:

• The CPU
• The memory controller
• The design of the Printed Circuit Board (PCB)
• The number of physical memory connectors
• The amount of memory soldered on

Therefore, at first sight, it may seem that a 32-bit address register matches perfectly with a 2^32 byte or 4 GB physical memory.

However, with that long an address register, you can address much more than 4 GB, just like the PAE does.

Looking at it in the other way, you can access 4 GB of memory address even with less than a 32-bit address register.

## Where is the Memory Address Register?

Being the special register on the CPU, the address registers holding the memory addresses are typically located inside the Central Processing Unit, or, to be more precise, on the memory processing component and helps to control the region from where the information is fetched.

## Conclusion

So, you see that the address register is a very important component of the CPU because it contains the address of the chosen memory words.

It is the place from where the memory is fetched by the following clock cycle to move it to the destination register or buffer, whatever is assigned to it.