Pipeline Flushing

What is Pipeline Flushing?

A pipeline flush is typically a process followed by the CPU of a computer to clear the pipeline when things get stalled.

Also known as a pipeline stall or a pipeline break, this happens when the CPU feels that it cannot process the instructions in the pipeline correctly any more in the following clock cycle.

Understanding Pipeline Flushing

Understanding Pipeline Flushing

Pipeline flushing refers to the process where the CPU flushes the problem-causing instructions from the pipeline.

The process clears it to ensure that the future calculations can be done easily without any interruptions or bottlenecks.

Typically, a CPU needs to process any given instruction while going through multiple stages, which are typically called machine cycles. These different stages are:

There can be multiple instructions stored in the pipeline that may be in different stages of the said machine cycle at a given point in time.

In the case of a pipeline stall, data may have to be brought in from the cache.

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And if it is not there, or, in other words, if there is a cache miss, the data will have to be fetched from the memory. This will cause a significant delay in the instruction processing function.

In such a situation, when there are two instructions that are dependent on data belonging to the same set in the memory, a bottleneck may be created, if these two instructions are not in the right sequence and are not processed simultaneously. This situation is called a data hazard.

Pipeline flushing ensures that there are no instructions in between them to interrupt the final process and, therefore, prevent causing a data hazard.

The performance level of a CPU can be reduced through pipelining if there are program transfer instructions such as CALL, JMP, RET and conditional jumps present.

These can cause a change in the sequence which will make all the instructions stored in the pipeline unacceptable after a program transfer instruction.

For example, if there is a conditional jump at a specific target address and the instructions that entered the pipeline after the transfer are invalid, a new sequence will be required to be loaded in.

If nothing is done to do away with the invalid instructions, it will create a bubble in the pipeline which will prevent the reloading of any new work instructions. This is what pipeline flushing does.

Pipeline flushing can be done in several ways. For example, in short pipelines or simple implementations, the instructions will be typically committed.

This means that it will write a modification that is architecturally visible. This is usually done when the instruction is guaranteed not to be in a branch shadow or a load that can fault any more.

On the other hand, if the CPU is very complex in particular that typically comes with out-of-order cores and longer pipelines, a specific technique called register renaming is followed.

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This process has some significant features and benefits offered such as:

Apart from that, the CPU can use its mechanism to either restore the state in the case of a flush or simply commit the transitory results to the architectural registers.

However, in this case it has to have a guarantee that the results will not be flushed anymore.

What is the Need of Pipeline Flushing?

The pipeline needs to be flushed or emptied, and the CPU should detect it as empty, so that it can execute a conditional logic or a jump, and carry on working with the next instructions uninterruptedly.

Pipeline flushing is often required when predictions are made incorrectly or there are instructions in them that may have a much higher impact than just causing instruction delays.

Ideally, there are lots of math tricks that the CPU may follow in order to lower cycle times and optimize processing of instructions.

These are really neat, but in most cases, it all depends on how predictable the next step is.

Normally, a CPU cannot check an instruction without carrying it out.

That is why only a few specific types of commands are stored in the pipeline, especially those instructions that are not completely predictable in particular.

For example, conditional logic is not predictable. The processor, therefore, simply follows the instructions, but if there are unfinished businesses in the pipeline when the CPU discovers a command, it will not be able to work.

Sometimes, the processor may execute a near jump, which is not considered as a conditional jump by the CPU. In such a situation, the processor may continue pipelining.

However, in the situations where the CPU needs to make a far jump, it will actually need flushing the pipeline.

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This is because it will create some real issues when and if there are instructions like JNZ or ‘Jump if not zero’ in the middle of the stream of instructions.

Such a situation will need all preceding instructions to be executed and completed as well as the flag register is uniform in a known state so that the instructions can be processed.

Once again, even in such situations bubbles or effectively NOP instructions will be inserted into the pipeline until it is flushed.

Few processors, such as Intel Pentium, use Dynamic Branch Prediction scheme, where an assumption is made regarding the branch instructions that are residing in the pipeline currently.

If this prediction turns out to be correct, then there will be no clock cycles lost and the pipeline will not need to be flushed.

On the other hand, if the prediction turns out to be incorrect, the pipeline will be flushed or cleared and things will start over with the right instruction.


Pipelining flushing is the process by which the instructions that are currently in flight and are associated with an erroneously predicted conditional branch are cleared.

This process ensures that the CPU performs at its optimized level and that instructions are executed quickly since there is no loss of machine cycles.