Silvermont Processor

What is Silvermont Processor?

The Silvermont processors refer to the codename of the 22 nm microarchitecture of Intel and belong to the system on chips from the Atom family. Technically, this is an architecture that supports low-power Atom, Pentium and Celeron branded processors.

The Silvermont processors come with 2 to 8 cores, a 12 to 14 stage pipeline, several instruction sets and an integrated HD graphics processor that itself supports a lot of different technologies and operates at a reasonably high frequency.

Understanding Silvermont Processor

What is Silvermont Processor

Silvermont is the codename of the microarchitecture used to design low-power processors of different brands, such as Atom, Celeron and Pentium, and to be used in the System on a Chip (SoC) made by Intel.

This successor to Saltwell and Bonnell is specially designed for using in smaller devices such as:

Silvermont basically forms the foundation for a total of four SoC families, such as:

However, here is the further breakup of these families, with some additional information.


There are a slew of innovative features included in these processors that also help in improving the power efficiency and performance level of them in comparison to their predecessors.

Some of these useful features are:

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All these features allow executing more instructions in quick time, which almost doubles the eventual throughput, because it does not have to wait for the earlier instructions to be completed to start executing the new one.


There are lots of features in Silvermont that are apparently borrowed from Westmere, but if you look at the instructions in particular, there are lots of additional instructions included in the design.

Some of these instructions are:

Memory hierarchy

The memory distribution in the Silvermont processors is also quite significant and worth noting.

The features of the Level 1 instruction cache are as follows:

The features of the Level 1 data cache are as follows:

The features of the Level 2 cache are as follows:

There is no Level 3 cache, however.

The details of the Random Access Memory supported by the Silvermont processors are as follows:


The Silvermont processors also support a pipeline using a dual-issue design like its predecessor, the Saltwell, but it is 2 stages shorter and the branch misprediction penalty is also 3 cycles lower.

The general features of the Silvermont pipeline are:

As said earlier, the Silvermont microarchitecture supports OoO execution, which enhances the speed of instruction execution and lowers latency.

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Ideally, the design of this microarchitecture allows the pipeline for decoding and issuing two instructions and dispatching five operations in one single cycle.

Stages of the Pipeline

The different stages of the pipeline are used to carry out different processes as follows:

Instruction Fetch

As it was in the earlier microarchitectures, the instruction fetch process takes up the initial three stages of the pipeline.

However, in the Silvermont architecture, the instruction fetching and ranch prediction processes are much more aggressive due to the introduction of the Out-of-Order Execution.

This means that the instructions in the Silvermont architecture will not get stalled and will not clog the whole pipeline, as they did in the case of its predecessor, the Saltwell.

Instruction Decode

Once again, in the earlier generations of microarchitectures, instruction decoding was a bit of a problem.

This is because approximately 5% of instructions are split up into micro-ops by the common software code.

On the other hand, in Silvermont, this is even brought down to as little as 1 or 2%. It is due to this reduction in the amount of micro-ops it translates into the performance of the processors directly.

The level of performance is significantly increased due to the fact that not less than 3 to 4 additional cycles are eliminated from the overhead.

There is also a second branch predictor in Silvermont, which helps it in making more precise predictions according to the information that is not known earlier.

It can be the information regarding the target address from the register or the memory or any other. This helps to override the generic predictor.

There is no need to worry about branch misprediction because the cost of it is also reduced in the Silvermont processors.

This is due to the fact that in this architecture, the branch misprediction penalties are lowered by 3 stages, down to 10 cycles, as opposed to 13 cycles in its predecessor, Saltwell.

Branch Prediction

There are two branch predictors in Silvermont that help in the branch prediction process as follows:

Here, the second predictor is responsible for controlling the process of speculative instruction issuance.

As for the first predictor, the Silvermont architecture allows for the use of the Branch Target Buffer or BTB in order to figure out the following fetch address, which may even include a 4-entry Return Stack Buffer.

This helps significantly in handling the calls and returns.

Integrated Graphics Processor

Some of the Silvermont processors come with an integrated graphics processor in them. For example, the Silvermont processors that support an HD Graphics (4 EU) include brand names as follows:

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The smartphone processors also come with an integrated graphics processing chip that supports an operational frequency ranging between 400 MHz and 64 MHz, depending on the model of CPU.

Depending on the version and type of the HD Graphics Processing Unit, they offer different types of support, such as:

General Information

To round up every technical and physical aspect of the Silvermont processors and the architecture, here is the complete rundown of it with some general facts and information summarized for you:


The Silvermont architecture is suitable for designing processors to be used in different small devices, such as smartphones and tablets.

However, the features and functionalities of these processors, along with their architectural support, allow them to be used in server and desktop computers as well.