Sunny Cove Processor

What is Sunny Cove Processor?

The term Sunny Cove refers to the codename given by Intel’s to the processor microarchitecture built on Intel 10 nm FinFET technology node that succeeded the Palm Cove microarchitecture.

Technically, this is a high-performing x86-64 core architecture that supports Dynamic Tuning 2.0 to sustain turbo frequencies for a long time, hardware acceleration, new subsets of AVX instructions, rebalanced execution ports, and a larger scheduler with large dispatch.

Understanding Sunny Cove Processor

What is Sunny Cove Processor

Sunny Cove is the microarchitecture designed and manufactured by Intel.

It is designed by the Research and Development Center of Intel in Haifa, Israel, on 10 nm FinFET technology and was launched in September 2019.

According to Intel, the prime focus while designing the Sunny Cove microarchitecture was on a few specific aspects, such as:

The design of the Sunny Cove allows using it in a wide range of client and server products, such as:

The Sunny Cove microarchitecture is the direct successor to mobile Palm Cove and server Skylake processors and predecessors of mobile Willow Cove and server Golden Cove processors.

Typically, this architecture is integrated in different Intel designs.

For example:

There is, however, no product featuring Sunny Cove for desktop computers.

You will need to use the Cypress Cove processors for that matter, which is actually a variant of the Sunny Cove microarchitecture, but reversed to the 14 nm technology node of Intel.

Pipeline

The Sunny Cove architecture supports a pipeline with the following features and capabilities:

Front-end and Back-end

The front-end of the Sunny Cove processor architecture is also quite improved in comparison to its predecessors, just like the back end.

As for the front-end, the following features are quite significant:

And, as for the back-end, the features are as follows:

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Instruction Set Architectures and Extension Support

The Sunny Cove architecture supports x86-64, x86 Instruction Set Architecture (ISA) along with a wide array of their extensions, both new and old, such as:

In addition to the AVX, or Advanced Vector Extensions, along with the AVX2 instructions, the Sunny Cove architecture also supports quite a few additional AVX-512 extensions as follows:

Apart from that, there are also a few other new instructions supported by the Sunny Cove architecture as follows:

And only the server parts of the Ice Lake variant support special features and instructions such as:

Memory Subsystem

The memory of the Sunny Cove processors comes with divisions such as L1, L2, and L3, each with different features.

The L0 µOP cache is divided statically in each core between the threads and is inclusive with the L1 instruction cache. It comes with the following features:

The Level 1 instruction cache is shared by two threads per core and comes with the following features:

The Level 1 data cache is also shared by the two threads per core and comes with the following features:

The Level 2 cache of the Sunny Cove processors for server and client come with slightly different features.

As for the clients, the features are as follows:

As for the servers, the features are as follows:

And the Level 3 cache of the Sunny Cove processor comes with the following features:

Translation Lookaside Buffer

The Sunny Cove architecture also supports different Translation Lookaside Buffers or TLBs, which consist of the following:

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In addition to that, there is also an additional and unified L2 TLB or Second-level or Shared Translation Lookaside Buffer (STLB).

The ITLB supports two types of page translations in different ways.

As for the 4 KiB page translations, the ITLB allows the following:

As for the 2 MiB or 4 MiB page translations, the ITLB allows the following:

The DTLB of the Sunny Cove architecture supports loading and storing in different ways.

For the load operation, the DTLB allows three different types of page translation in different ways.

For example, for 4 KiB page translations, the DTLB allows the following:

For 2 MiB or 4 MiB page translations, the DTLB supports the following:

And for 1G page translations, it allows the following:

For store operations, the DTLB supports all pages and allows the following:

As for the additional STLB, it supports 16-way set associative, 2048 entries for all pages. And, when it comes to partitioning operations, the STLB allows the following:

Scheduler Ports

The Sunny Cove processors come with an enlarged scheduler with two additional ports.

All these ports have a specific purpose to serve during the memory operations. All these are wider and can dispatch up to ten operations in every cycle.

If you consider the arithmetic perspective of the execution engine, the functionality is boosted by the four workhorse ports.

If you consider the vector point of view, the performance of the Sunny Cove is retained by the three FMAs and ALUs.

However, the addition of another shuffle unit on Port 1 is a significant change in its architecture which allows easy moving of data within the register.

Some of the ports of the scheduler may be designated for multiple purposes, while a few may serve a single purpose.

Here is the detail of the designation of the different scheduler ports.

The Port 0 of the scheduler is designated for the following:

The scheduler Port 1 is designated for the following:

Port 2 and Port 3 are designated to load AGU.

Port 4 is designated to store data.

The Port 5 of the scheduler is designated for the following:

The Port 6 is designated for the following:

Port 7 and Port 8 are designated to store AGU.

The Port 9 is designated to store data.

Execution Units

There are several different types of execution units in the Sunny Cove processors, and each of them is vested with the responsibility to carry out different instructions.

Here is the breakdown of the execution units with their numbers and the types of instructions carried out.

There are four ALUs that carry out the following instructions:

There are two SHFT units that carry out the following instructions and more:

There is only one Slow Int unit that carries out the following instructions and more:

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There are two BM units that carry out the following instructions and more:

There are three Vector ALUs that carry out the following instructions:

There are two Vec_Shft units that carry out the following instructions:

There are two Vector Add units that carry out the following instructions:

There are two Shuffle units that carry out the following instructions:

There are two Vector Mul units that carry out the following instructions:

There is one SIMD Misc unit that carries out the following instructions:

There is one FP Mov unit that carries out the following instructions:

There is one DIVIDE unit that carries out the following instructions:

Additional Comparative Improvements

So, with all these design aspects, the Sunny Cove processors offer better performance in comparison to their predecessors. There are also a few other relative improvements in this architecture that further add to its capabilities. These improvements are as follows:

Sunny Cove vs Willow Cove

Conclusion

The Sunny Cove processor comes with significant improvements over its predecessors, Skylake and Palm Cove processors, and is integrated into a wide variety of Intel designs.

With major uplift in the Instruction per Cycle and better front-end and back-end, the performance of them is increased significantly.