Willow Cove Processor

What is Willow Cove Processor?

Willow Cove refers to the codename given by Intel to the processor microarchitecture that succeeds the Sunny Cove architecture. Released in September 2020, these processors are fabricated on the 10 nm SuperFin process node of Intel, or 10 SF.

Technically, the Willow Cove x86 core microarchitecture powers the Intel Core mobile processors belonging to the 11th generation, codenamed Tiger Lake.

Understanding Willow Cove Processor

What is Willow Cove Processor

The 10 nm SuperFin Willow Cove x86 core microarchitecture designed by Intel succeeds Sunny Cove and offers better and higher performance.

It is used in a wide range of client and server products, including Tiger Lake cores.

Though there are some features similar to its predecessor, the Willow Cove architecture supports improved features to offer a 10% to 20% enhancement in performance. These include the following:

Some of the other notable improvements in the architecture design of the Willow Cove processors are:

As said earlier, Willow Cove is the successor to Sunny Cove and the predecessor of Golden Cove.

Therefore, as a successor to Sunny Cove, it is quite natural that it will have some notable changes in its architecture in comparison.

A couple of such changes are:

SuperFin Frequency

One of the most significant aspects of the Willow Cove architecture is the improvement in the process node.

Moving onto 10 SF and using a set of new SuperFin transistors offers the Willow Cove processors much higher scalability in terms of frequency and voltage.

This in turn offers better and much higher performance metrics at the same voltage across the board as compared to the predecessor of the Willow Cove architecture, Sunny Cove.

This, in turn, helps the processors to perform at a higher peak frequency of about 5 GHz as opposed to the 4 GHz of its predecessor, if the peak voltage remains the same.


The pipeline of the Willow Cove processors comes with the following features:

Cache Subsystem

The Willow Cove processors come with L1, L2 and L3 cache, and each of them offers a significant edge to its performance in its own distinct way.

For example, the Level 1 cache measures 80 KB per core, where 32 KB is reserved for instructions and 48 KB for data.

The Level 2 and Level 3 cache sizes are however much larger in comparison to its predecessor. For example:

The more L2 and L3 memory in the cache structure surely adds up to its performance, but there are also some worthy tradeoffs.

For example, the non-inclusive, 150% larger, 20-way 1.25 MiB L2 cache may be the biggest update, but it comes at the cost of inclusivity.

Usually, with a cache measuring more than double, the miss rate will be reduced by √2. This means that the 2.5x large L2 cache will now have cache misses reduced by nearly 58%.

On the flip side, if you consider the latency aspect, the bigger caches seem to have much longer access latencies. This means that the L2 cache in this case will be a bit slow in its performance.

However, the non-inclusive nature offers a small additional gain in its performance because it will not need back-invalidation or maintain an identical copy of entries in the L2 cache.

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Still, it will have a knock-on effect on its power and die area. Moreover, additional hardware is required to be built for a non-inclusive cache into the core so that it complies with the rules for cache coherency.

And, most importantly, with the size of the cache increased, a non-inclusive cache cannot run at the speed of an inclusive cache.

As for the L3 cache, there is a notable increase in its capacity, but there is a reduction in its associativity. This is sure to affect the performance.

Control Flow Enforcement Technology

As said earlier, CET or Control Flow Enforcement Technology is enabled in the Willow Cove architecture for added security.

This protects from attacks with respect to returns and jumps, and prevents diversion of the instruction stream to a code not sought for.

This technology is enabled by enabling Indirect Branch Tracking and Shadow Stacks, which prevent and protect against misdirected calls or jump targets and return addresses through page tracking, respectively.

However, it needs specific software built with new instructions.

Instruction Set Architecture and Extension Support

The Willow Cove processors supports x86-64 Instruction Set Architecture (ISA) along with a lot of other extensions, such as:

There are also a few new instructions introduced in the Willow Cove microarchitecture, as follows:

Willow Cove vs Golden Cove


The Willow Cove processors are built on the 10 nm manufacturing process and come with a redesigned Middle Level Cache.

It is designed to offer much higher frequencies as compared to its precursor at comparatively lower voltages.

This improves its power efficiency and helps it offer a better dynamic range overall.