SRAM Types and Its Operation Explained

There are different types of SRAMs available out there so much that you may be confused while making a choice especially if you do not know the types and their operation process.

Here in this article you will find the types of SRAMs categorized and explained explicitly in order to make you more knowledgeable. Therefore, continue reading.


  • There are different types of Static RAM modules available in the market such as NVRAM, PSRAM, asynchronous SRAM, and synchronous SRAM.
  • Static RAM modules may also be categorized according to their features and some of them may also come integrated into the microcontrollers.
  • Irrespective of the type of the Static RAM, their operation is pretty simple which is basically storing the value in a selected cell to write in the cross coupled flip-flops.

What Are SRAM Types and Its Operation?

SRAM Types

There are different types of Static Random Access Memory available and these are categorized according to their designs, functions, features and other parameters.

A few of these types of SRAMs are:

Non-volatile Static RAM

Also called as NV-SRAM, these types of memories follow the standard Static RAM functionalities. However, they do not lose the data when the power supply is lost or the computer system is turned off.

This ensures preservation of crucial data and information. These NV-SRAMs are used in a wide range of applications such as:

  • Networking
  • Medical fields and
  • Aerospace to name just a few.

Ideally, these are used in those places where use of batteries is quite impractical but preserving data is extremely important.

Pseudo Static RAM

Also known as PSRAM more commonly, this type of memory comes with a DRAM storage core which is united with a self refreshing circuit.

Though it apparently seems to be a slower Static RAM, the cost advantage or density is much more in comparison to a true Static RAM.

Most importantly, in the Pseudo Static RAM there is no complexity as the Dynamic RAM when it comes to accessing.

Asynchronous Static RAM

These types of Static RAMs are categorized on the basis of their function and are typically not dependent on the clock frequency because in them the address transition mainly controls the data in and data out.

Asynchronous SRAMs were used extensively as the main memory in the 1990s to have faster access time especially in the cache-less, small and embedded processors. These processors were used in a wide range of applications including and not limited to:

  • Industrial electronics
  • Measurement systems
  • Hard disks
  • Networking equipment and more.

Synchronous Static RAM

In these types of memories the timing in most of the cases are set off by the clock edges.

The clock signals play a significant role in the synchronous Static RAM because the data in, address, and other control signals all are linked to it.

These days, the synchronous SRAM such as the DDR SRAM is used just as a synchronous Dynamic RAM.

Rather, it can be said that a DDR SDRAM is used more than an asynchronous Dynamic RAM.

The interface of the synchronous memory is quite fast because the access time can be reduced significantly with the use of pipeline architecture.

In addition, as the Dynamic RAM is quite cheaper as compared to a Static RAM, the DRAM often replaces the SRAM especially in those particular situations where a large amount of data is needed.

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Since this type of RAM is pretty fast for random access and not for burst or block access, it is used primarily as small on-chip memory, as CPU cache, FIFOs and other undersized buffers.

Integrated on Chip Static RAM

Sometimes, Static RAM may also be integrated into the microcontrollers as cache memory or RAM and it can range anywhere between 32 bytes and up to 128 kilobytes.

In some cases it can also be integrated into powerful microprocessors as their primary caches such as those belonging to the x86 family and several others, and can range anywhere between 8 KB and up to several megabytes.

A few other specific integrated uses of the Static RAM include:

Feature-wise Categorization

As said earlier, Static RAM can be categorized on the basis of their features and some of them are:

  • ZBT or Zero Bus Turnaround Static RAM – In these SRAMs the turnaround or latency between read and write cycles which is the number of clock cycles taken to change the access to the SRAM from read to write and vice versa is zero.
  • Synchronous Burst Static RAM – Also known as syncBurst SRAM or simply syncBurst, the features of this specific type of RAM increases the write operation of the Static RAM.
  • Double Data Rate Static RAM – Also known as DDR SRAM, the features of them are synchronous, Double Data Rate I/O, and single read/write port.
  • Quad Data Rate Static RAM – These are synchronous RAM and come with quadruple data rate I/O and separate read and write ports.

Based on Transistor Type:

The Static RAMs can also be categorized on the basis of the type of transistors they have such as:

  • Bipolar junction transistor based memory that are quite fast but consumes high power and used in TTL or Transistor-Transistor Logic and ECL or Emitter-Coupled Logic and
  • MOSFET or Metal Oxide Semiconductor Field Effect Transistor that is most commonly used today and consumes very low power.

There are also some other types of flip-flop Static RAM such as:

  • Binary SRAM and
  • Ternary SRAM.

However, whatever be the type of the Static RAM, there are a few specific characteristics of it that makes it quite useful and distinguishable from Dynamic RAM as well. These are:

  • Their size
  • Their power consumption
  • Their usability as Level 1 or Level 2 cache
  • Their lower cycle time than DRAM since they do not have to break in between accesses and
  • They are mainly used as cache memory.

Therefore, as you can see, there are different types of Static RAM that can be used in different areas but is used usually for the same purpose, which brings to the next section of the article – its operation.

SRAM Operation

Typically, the operation of the Static RAM memory cell is comparatively straightforward which usually involves selecting a cell and storing the value to be written in the cross-coupled flip-flops.

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Each of these cells can be addressed individually and are prearranged in a matrix.

Most of the time, the Static RAM memories select a complete row of cells at one time and then read out the entire contents of all those cells in a row and column line.

It is not always necessary to use two bit lines while using the signal and its converse but this is a usual practice because it helps in improving the data integrity and noise margins.

When two same lines are used, however, the system will realize that there is a problem and will automatically re-interrogate the cell.

While using two bit lines, these are passed on to two separate input ports on a comparator.

This helps in identifying the differential data mode that needs to be accessed. It also helps in identifying any minute swings in the voltage more accurately, if present.

However, it is the word line or WL that allows access to the memory cell of the Static RAM. It also controls the two access control transistors.

These access control transistors are in charge of determining whether or not the memory cell should be linked with the bit lines.

The two bit lines are typically used for transferring data in both the read and write stages of the operations of a Static RAM.

Different Stages of Operation

The operation of the Static Random Access Memory involves three particular states such as:

  • The standby state where the circuit remains idle
  • The reading state where the data is requested and
  • The writing state where the contents are updated.

Typically, when the SRAM operates in the read and write modes it typically needs to encompass readability and write stability.

Here is the brief description of the three different states of operation of a Static RAM.


In this state the word line is not affirmed and the cell is disconnected from the bit lines by the M5 and M6 transistors.

On the other hand, the two cross-coupled inverters that are created by the M1, M2, M3, and M4 transistors typically keep on reinforcing each other till the time they are linked to the supply.


In this state of operation, practically, there are two things required in general. These are:

  • Asserting a Word Line WL and
  • Reading a cell state of the SRAM by a single access transistor as well as the bit line.

This is not done as easily as it is said because the bits lines are comparatively long.

Add to that, the bit lines also have quite a high parasitic capacitance.

Therefore, it is needed to expedite the reading process, which, by itself, is quite a complicated process used in practice.

The read cycle involves different processes such as:

  • Both the bit lines are pre-charged first to high or logic 1 voltage
  • Then the word line WL is asserted in order to enable both of the access transistors M5 and M6 causing one bit line voltage to drop a bit and
  • Then the sense amplifier identifies the difference in the voltages of the bit lines and determines whether the line with a higher voltage had 1 or 0 stored in it.

This complete read operation will be fast if the sensitivity of the sense amplifier is higher.

However, the pull down is much easier because the NMOS or the N-channel Metal Oxide Semiconductor is more powerful.

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As for the writing operation of the Static RAM, the cycle starts with the application of the value to the specific bit lines that need to be written.

For example, if it is written to be a 0, then a 0 is to be applied to the bit lines.

This means that BL to 1 and BL to 0 are to be set. This process is pretty much the same as setting a reset pulse to the Set/Reset or SR-latch which results in the change of state of the flip flop.

On the other hand, when a 1 is to be written, the values of the bit lines are simply inverted. WL is asserted and the value which is needed to be stored is latched in.

The strong design of the bit line input drivers makes this type of writing possible.

These drives can override the prior states of the cross-coupled inverters very easily in comparison to the comparatively weak transistors present within the cell itself.

However, in practice, NMOS transistors M5 and M6 for access need to be stronger in comparison to the bottom NMOS M1 and M3 transistors or the P-channel Metal Oxide Semiconductor or PMOS M2 and M4 transistors, especially if they are of the same size.

As a result, when a specific pair of transistors, such as the M3 and M4 is overridden only a bit by the write process, the gate voltage of the other pair of transistors, such as the M1 and M2 is also altered.

This implies that both the transistors M1 and M2 can be overridden easily and it also helps the cross-coupled inverters by a great deal to amplify the whole writing process.

The behavior of the bus also plays a significant role in the overall operation of the Static RAM.

As you may know that the output of a RAM typically depends on the access time.

This means that a RAM that has an access time of 70 ns will deliver valid data within 70 ns from the time of validation of the address line.

However, there are a few specific types of Static RAM cells that come with a ‘page mode’ feature where the 256, 512, or 1024 words of a page can be read in sequence with a considerably shorter access time, often as less as 30 ns approximately.

However, the page in this case is chosen by setting the upper address lines.

The words of the page are then read sequentially, treading through the lower address lines.


So, that is all about the types of Static RAM and their reading and writing operations that you need to know.

With such improved knowledge gained from this article it will not be difficult for you to determine whether you should use a static or a dynamic RAM in your computer for better performance.

About Dominic Cooper

Dominic CooperDominic Cooper, a TTU graduate is a computer hardware expert. His only passion is to find out the nitty gritty of all computers since childhood. He has over 12 years of experience in writing, computer testing, and research. He is not very fond of social media. Follow Him at Linkedin