A lot of data and information travels through the different components in a computer when you use it. These signals, information and data are transmitted through different interfaces, buses or connectors. One such is the PCI or Peripheral Component Interconnect bus.
The PCI comes with different bus variations and each of these follow a different technology to operate. For someone who likes technicalities, it is important to know about the different bus variations in PCI as well as the technology that they run on.
In This Article
- The PCI bus technology allows adding as many as five external devices via the connectors that can be alternated with two permanent ones on the motherboard.
- The design of the PCI bus includes a front side bus and a backside bus where the former connects the CPU to the other parts of the computer and the latter connects the Level 2 cache to the processor.
- There are different varieties of PCI buses such as conventional PCI, PCI-X, and PCI Express.
- The performance of the PCI bus typically depends on different parameters such as the clock speed, bus width, data rate, voltage signals and slots.
What is the Technology Behind PCI Bus Variation
If you compare a PCI or Peripheral Component Interconnect with the VL-Bus or VESA or Video Electronics Standards Association Local Bus, the former is able to connect much more devices than the latter.
In fact, it can connect up to 5 external devices.
Moreover, each of the five connectors that are used to connect these devices externally can be substituted with two permanent devices on the motherboard.
Add to that, on the same computer you can connect more than one PCI bus. However, this is seldom done by the users.
The Peripheral Component Interconnect bridge chip usually controls the speed of the bus with no relation to the speed of the CPU or the Central Processing Unit.
This ensures that there is a high degree of reliability in the system which is mainly due to the fact that the manufacturer of the PCI hardware knows what exactly it should be designed for.
Typically, the Peripheral Component Interconnect bus comes with a small number of pins. It is the technology underlying the PCI bus that allows it to work with so few pins.
The main reason behind it is that the technology allows hardware multiplexing.
This normally refers to the process in which the device transmits more than one signal through a single pin.
The PCI technology also supports devices that use either 3.3 volts or 5 volts.
The design of the PCI bus has two sides namely the front side bus and the backside bus.
The front side bus refers to the physical connection that allows connecting the processor of the computer to almost all other components in it such as:
- The hard drives
- The main memory or RAM and
- The PCI slots.
Ideally, the front side bus of the Peripheral Component Interconnect can operate at a speed of up to 400 MHz but it is simply double that in the newer systems.
On the other hand, the backside bus of PCI sets up an entirely separate connection between the Level 2 cache and the processor of the computer.
This particular bus has a higher operating speed in comparison to the front side bus, which is normally the same speed of the processor of the computer itself.
This ensures that there is better performance and more efficiency in the caching tasks.
The design of the backside bus of the PCI has changed over the years.
For example, in the 1990s, this backside bus connected the main processor of the system with just a wire to the off-chip cache.
However, after that, there was a change in the design and the Level 2 cache was included into the main processor.
This made the CPUs much smaller in size and cheaper to make.
With reference to this context only, yes, you can say that the backside bus of the Peripheral Component Interconnect is not a bus in the true sense anymore.
PCI Bus Variants
Well, the difference in the Peripheral Component Interconnect buses is usually determined by the variety of the PCI such as the Conventional PCI, PCI-X and PCI Express.
This is supposed to be the indigenous PCI Revision 1.0 local bus. The specification of this bus was launched in June 1992.
However, the industrial initiation of this particular technology commenced from April 1993 with the PCI Revision 2.0.
The unique features of this revision included:
- A clock rate support of up to 66 MHz and
- Inclusion of expansion slots.
Then with the PCI Revision 2.1 introduced in June 1995, the PCI bus came with noteworthy improvements with respect to the bandwidth efficiency and the 66 MHz clock rate.
Further down in December 1998, the Revision 2.2 was launched which came with some of the detail issues spelled out.
And, in the next Revision 2.3, the specification for 5 volt add-in cards was missing but the specification for 5 volt system connectors was retained.
The final Revision 3.0 of the Conventional PCI bus did not have the specification for 5 volt system connectors and it also ruled out the use of 5 Volt add-in cards as well.
However, in spite of all the revised versions, the Conventional PCI bus can be still characterized by:
- A clock speed ranging between 33 MHz and 66 MHz and
- A bus width of 32 bits or 64 bits.
You will find any combination in a Conventional PCI bus in terms of speed and bus width which is why you will find that a huge majority of the desktop computers are equipped with the Conventional PCI technology.
The PCI-X is considered to be a significant evolution of the Conventional PCI bus that promises a high performance.
Typically, in its Revision 1.0 that was launched in July 2000 it was specified that the PCI-X is an addition to Conventional PCI.
The hardware structure of this particular technology is the same as the Conventional PCI.
This means that you can use a PCI-X add-in card in the slot of a Conventional PCI and vice versa.
However, the PCI-X bus typically comes with a much higher bandwidth in comparison to the Conventional PCI bus.
In addition to that, the PCI-X bus is characterized by a superior clock speed which can go as high as up to 133 MHz.
The PCI-X bus is normally found with a bus width of 64 bits but it does not mean that the ones with 32 bit bus width do not exist anymore.
However, a lot of improvements were made to the PCI-X over the years and some of the enhanced features were noticed in the PCI-X Revision 2.0.
One of the most significant improvements in the features is that the clock speed was extended by a significant margin than what it was in the earlier versions.
Ideally, the PCI-X bus technology is designed to be used in the server applications and that is the most significant reason that you will find this technology in several of the high-end motherboards for computers.
The PCI Express technology is the latest and it is considered to be a substitute of the Conventional PCI bus.
It offers a lot of flexibility and a much better performance and at the same time it ensures that the software compatibility is maintained.
In this specific technology, the hardware bus structure is different by a large extent though the card form factor of the current desktop enclosures is retained.
The connector however has changed and the PCI Express utilizes a point-to-point technology which is serialized rather than parallel and supports enormous data transportation.
The performance of the PCI bus can be characterized on different parameters.
The most significant parameters that influence the performance of the bus directly are as follows.
The bus width refers to the transmission medium that is utilized by the Peripheral Component Interconnect bus.
It is usually a set of 32 or 64 parallel electrical lines.
Typically, this means that a basic block of either 32 bits or 64 bits will be transferred through the PCI bus for the source agent, known as the initiator to the destination agent, known as the target, in every clock cycle.
In terms of bytes, a data of 32 bits can be taken as a set of 4 bytes and that of 64 bits can be considered as a set of 8 bytes.
The clock speed of the PCI bus is another useful parameter that determines the performance of the system.
Ideally, a PCI bus is considered to be a synchronous system which means that each of the agents that is linked to the bus is activated by a clock signal which demonstrates the similar phase and frequency.
As said earlier, the clock speed of the Conventional PCI is either 33 MHz or 66 MHz, and that of the PCI-X bus is 66 MHz or 133 MHz.
Ideally, the principle used for data transfer by these Peripheral Component Interconnect buses involves transferring data in large amounts at the clock speed.
There may be long data bursts and the agents with whom the data is exchanged with, should cooperate and respond to it.
It is a dual process and when both the participants cooperate with each other, they are called the ‘good citizens.’
The clock speed actually indicates the capability of data throughput of the PCI bus but is the good citizenship of the participating agents that the high performance and large data transfer is subordinated to.
And, yes, it also depends on the performance and support of the motherboard of the system itself.
Data rate refers to the speed of data transfer and it is also known by different terms such as bandwidth and throughput.
Data can be transferred at any given time between the initiator agent and the target agent and the entire transaction does not last for more than a couple of microseconds.
This is because there may be another agent waiting with a request of its own to transfer data.
The bus ownership should be assigned to all of the requesting agents in a precise manner to ensure that all of the pending transactions of data between the different initiator and the targets are effectively satisfied.
An arbitration process is used for this which assigns the bus ownership successively.
This means that there can be a difference between the practical data rate and the effective data transfer rate over the Peripheral Component Interconnect bus.
Ideally, the peak data rate is reached only within a data burst for a very short period of time.
And, in reality, the practical data rate will be much lower than this peak data rate which is just a theoretical figure.
The actual data rate is estimated by taking the average of all transactions for a considerable period of time.
The result is usually denoted in MB/s or Megabytes per second.
Attaining full speed bursts in a sustained manner is just a means for the practical data rate to move toward the peak data rate.
However, there are several different considerations to make for this such as latencies of transaction arbitration.
These factors typically restrict the utility of the peak data rate.
However, several test results and survey reports establish that nothing in excess of 70% of the peak data rate should be expected as the practical data rate.
This means that the practical data rate will always be much lower in comparison to the peak data rate of any given variant of Peripheral Component Interconnect bus.
For example, considering the different configurations of different Peripheral Component Interconnect buses, the difference between the peak data rate and practical data rate can be summarized as follows:
- For Conventional PCI buses only with a clock speed of 33 MHz and a bus width of 32 bits or 4 bytes, the peak data rate will be about 132 MB/s and the practical data rate will be nearly 90 MB/s
- For Conventional PCI buses only with a clock speed of 33 MHz and a bus width of 64 bits or 8 bytes, the peak data rate will be about 264 MB/s and the practical data rate will be nearly 180 MB/s
- For both Conventional PCI or PCI-X buses with a clock speed of 66 MHz and a bus width of 32 bits or 4 bytes, the peak data rate will be about 264 MB/s and the practical data rate will be nearly 180 MB/s
- For both Conventional PCI or PCI-X buses with a clock speed of 66 MHz and a bus width of 64 bits or 8 bytes, the peak data rate will be about 528 MB/s and the practical data rate will be nearly 360 MB/s
- For PCI-X buses only with a clock speed of 133 MHz and a bus width of 32 bits or 4 bytes, the peak data rate will be about 532 MB/s and the practical data rate will be nearly 360 MB/s and
- For PCI-X buses only with a clock speed of 133 MHz and a bus width of 64 bits or 8 bytes, the peak data rate will be about 1064 MB/s and the practical data rate will be nearly 720 MB/s.
Looking at the different values of peak data rates and practical data rates, you can yourself deduce that both the rates are doubled when the bus width is doubled.
However, if you need to calculate the peak data rate arithmetically for any other type of Peripheral Component Interconnect bus you will need to multiply the number of bytes that make up that particular data width with the clock speed.
This should be considered as the rule of thumb in this particular matter which will eventually help you to determine the performance level of the system overall.
However, at this point, you should remember that the real performance of the system will basically depend on the characteristics of it.
It is for this reason it is recommended that such evaluations are not made theoretically, but for better and more accurate results, it should be confirmed on a real system.
Typically, every personal computer and server motherboard are able to support extra internal hardware when it is needed to satisfy a number of specialized peripheral tasks such as frame grabbers.
The most productive and common way to achieve this feat is by using a peripheral bus, especially the PCI bus.
Ideally, the Peripheral Component Interconnect bus technology comes as a set of slots.
All these slots that you may find in a PCI bus are usually connected in parallel.
This specific design allows the users to use add-in cards on each of these multiple slots.
This in turn allows them to connect added peripheral functions.
However, the number of slots in a PCI bus cannot be exceptionally high due to electrical reasons.
It is actually the standard of the PCI bus that dictates the number of slots that a PCI bus is exactly permitted to expose.
Typically, the design of the modern motherboards allows them to support more than one bus even if they come with varying attributes.
Depending on the respective designs, here is an example of individual bus offered by the motherboard:
- It is four for Conventional PCI bus only with a clock speed of 33 MHz
- It is two for Conventional PCI bus only with a clock speed of 66 MHz
- It is four for PCI-X bus with a clock speed of 66 MHz and
- It is two for PCI-X bus with a clock speed of 133 MHz.
However, if the operation is performed at a clock speed of 66 MHz, it is the PCI-X bus that is more favored in comparison to a Conventional PCI bus.
The main reason behind this is that the number of slots available in the former is simply double the number of slots available in the latter.
This is perhaps the main technical feature that justifies the preference of a PCI-X bus over a Conventional PCI.
If you do not know what a voltage signal or a signaling voltage is, then here it is.
A signaling voltage is the particular voltage level below which the PCI bus operates while transferring digital data through it.
This particular voltage level defines both the low logic states as well as the high logic states.
However, in order to understand the technological aspects in a much better way, it is better to consider two separate systems with reference to this context such as:
- One that operates at a 5 volt signaling environment and
- One that operates at a 3.3 volt signaling environment.
This will ensure that you do not mix up between the signaling environments.
Ideally, having the systems operate at different environment settings means that all add-in cards that are connected to a PCI bus will certainly have to embrace the signaling voltage that is supported by the motherboard.
Usually, if the 5 volt system is older, the 3.3 volt system will tend to replace it.
Moreover, the signaling voltage migration is the primary incentive for the revisions of the Peripheral Component Interconnect.
The slot variants also have a significant effect on the signaling voltage of the PCI bus.
Typically, in a PCI bus the slots or system connectors may come in two specific types such as:
- 3.3 volt and
- 5 volt.
However, slots of any particular type of PCI bus will be identical, needless to say.
But, as said earlier, the signaling voltage of 3.3 volts or 5 volts will be imposed by the motherboard of the computer system.
The technology and design of the 3.3 volt connector ensures that any bus that complies with any given type of PCI variant can exhibit it.
And, on the other hand, it is the design and technology on which a 5 volt connector is built that does not allow a bus that complies with a PCI-X or a Conventional PCI 3.0 to exhibit it.
Taking a look at the add-in card variants, their effects on the signaling voltage can be explained as follows.
Ideally, the design of a PCI board can be such that it may function in both a 3.3 volt environment or in a 5 volt environment.
However, when the PCI is able to operate in a 5 volt environment, it is usually and commonly referred to as a universal card.
Normally, there are 3 types of add-in cards that feature an edge connector shape and fit effectively into a permissible system connector.
- A 3.3 volt add-in card, which can be any card that complies with any PCI variant
- A universal add-in card, which excludes any add-in card that complies with PCI-X and
- A 5 volt add-in card, which excludes any card that complies with Conventional PCI version 2.3 or 3.0 as well as PCI-X.
Ideally, a 3.3 volt add-in card will support Conventional PCI up to 3.0 and PCI-X bus while the universal add-on card will support only Conventional PCI bus up to 3.0. And, as for the 5 volt add-in card it can support Conventional PCI bus up to 2.2.
In simple terms, interoperability refers to that feature that allows inserting an add-in card physically in a slot and it functions perfectly.
It is usually allowed irrespective of the width of the PCI bus which can be either 32 bits or 64 bits as well as the keying system.
Ideally, the add-in cards and the 64-bit PCI slots are differentiated by the supplementary assembly of contacts.
The PCI bus technology typically offers a larger degree of compatibility among the different variants which is no doubt a clear advantage provided by it.
However, there is a risk of putting in an add-in card of type A into a slot of type B because it may eventually cause a loss in the performance of the system overall.
This is mainly because any system performance will typically line itself up with the weaker device.
Bus Width Interoperability:
In PCI technology, when it comes to bus width interoperability, any combination is allowed. However, the data rate achieved in each case may be different.
This means that, when you put in a 64-bit board in a 32-bit slot, the rate of data transfer achieved may be half the data rate allowed by a motherboard which is 64-bit capable.
On the other hand, when you use a 32-bit board in a 64-bit slot, the performance of the card may not be tarnished but it is the capability of the motherboard that would go waste somehow.
Ideally, the data rate, which is expressed in megabytes per second, with respect to the motherboard should be considered to be double in terms of its input to the universal bus traffic.
These are some specific considerations that typically should be taken into account during the design stage of the system.
Signaling Voltage Interoperability:
When it comes to signing voltage interoperability, it is simply not allowed to mix 3.3 volt signaling voltage with 5 volt signaling voltage.
However, there is no chance of doing so because the keying system of the board as well as both the connectors will not allow you to do so.
Bus Variant Interoperability:
There is no doubt that the Conventional PCI and the PCI-X are both interoperable.
However, in the design stage of the system, there are a few specific considerations that need to be taken into account.
For example, a PCI-X compliant board will be able to function in two particular modes such as:
- In the PCI-X mode and
- In the Conventional PCI mode.
However, when you consider the Conventional mode, quite a few functional features that are provided by the PCI-X bus may not be available.
For example, for PCI-X slot compliance, when all bus boards are PCI-X compliant, the operating mode will also be that of PCI-X.
On the other hand, if even one board is Conventional PCI compliant, then the operating mode will be that of a Conventional PCI.
In the same way, for Conventional PCI slot compliance, if the board is PCI-X compliant, the operating mode will also be of a Conventional PCI just as it would be for a Conventional PCI compliant board in the same slot.
If you want to take full advantage of the PCI-X compliant board, you must ensure that you also choose and use a PCI-X compliant motherboard.
Apart from that, it is also needed to make sure that occupying the other bus slots is averted with the Conventional PCI boards.
However, when you use a Conventional PCI board in a PCI-X bus slot, the performance of it is not deteriorated.
Clock Speed Interoperability:
For any given Peripheral Component Interconnect bus, the clock speed is usually unique.
If the add-in cards and the system bus use a slower clock speed, it will automatically adapt to it. This way it will promise interoperability.
However, this can be dangerous as a system due to the fact that the performance of the data rate is directly proportional to the clock speed.
For example, if a 66 MHz board is inserted into a 66 MHz slot the data transfer rate will be reduced by a factor of two when a 33 MHz board is used in a different slot but with the same bus.
Typically, if the slot clock speed is 133 MHz, the operating speed will also be 133 MHz for all boards with a clock speed of 133 MHz.
And, if even one board comes with a lower clock speed, the operating speed will be the same as the clock speed of that board.
On the other hand, if the clock speed of the slot is 66 MHz, the operating speed will be 66 MHz for all boards that come with a clock speed of 66 MHz or higher and if at least one board comes with a lower clock speed, the operating speed will drop to the clock speed of that solitary low clock speed board.
And, if the clock speed of the slot is 33 MHz, then for all boards that come with a clock speed of 33 MHz or higher, the operating speed will always be 33 MHz.
Finally, it is the power voltage that needs to be discussed. Typically, a system that comes with the Peripheral Component Interconnect slots or connectors need to supply the necessary power through four different rails such as:
- +12V and
Here, you should not mix up the signaling voltage with the power voltage because both are not the same.
Ideally, all PCI system slots need to provide +5V and +3V3 power separately for the 5 volt or 3.3 volt signaling system.
However, some of the computer systems do not offer a +3V3 power supply rail even though they feature a PCI bus with 5 volt signaling environment. This causes potential interoperability issues.
This issue can be effectively overcome when the 5 volt and universal frame grabbers do not make use of the +3V3 power rail but extracts the required power from the +5V rail.
With every passing day, the computer technology is evolving at a breakneck speed in order to keep up with the demands of the users.
This has forced the PCI bus technology for its different variants to evolve as well from its de facto standard.
Such improvement in the PCI bus technology has resulted in different Peripheral Component Interconnect cards such as PCIe 4.x, PCIe 5.x, and more.
This has somewhat narrowed the development gap enhancing the already great potential of the PCI bus and its variants.
Now, reaching to the end of this article, you must be more knowledgeable about the PCI bus and cards and the technology underlying it, enough to deduce which particular card will support a slot in your system in the best possible way to produce a high data transfer rate.