In This Article
What is Amber Lake Processor?
- The Amber Lake processors are the mobile versions of the Kaby Lake microarchitecture, designed and manufactured by Intel.
- Released in the last quarter of 2018, these dual-core processors are built on the 14 nm fabrication process and have a multichip module chipset.
- It is typically a dual-core, four-thread processor and the clock rate achieved may range between 1.1 GHz and 15 GHz.
- The architecture of these processors is so designed that it allows them to be used in mobile devices needing extremely low power.
- The architecture of Amber Lake supports a 14-stage minimum and a 19-stage maximum pipeline that allows 5-way decoding.
Understanding Amber Lake Processor
The Amber Lake microarchitecture is a creation of Intel, released on August 28, 2018.
This successor to Kaby Lake and predecessor of Ice Lake are intended for use in extremely-low power mobile devices.
These processors typically have a dual-core configuration and have four threads in them to handle almost everything thrown at them.
Built on the 14 nm manufacturing process, the architecture supports a pipeline with the following features and abilities:
- Out-of-Order execution
- Speculative execution
- Register renaming
- A minimum of 14 stages
- A maximum of 19 stages
- 5-way decoding
Instruction Set Architecture and Extension Support
The architecture also follows the x86-64 Instruction Set Architecture (ISA) and the following extensions:
- MOVBE or Move Data After Swapping Bytes
- MMX or MultiMedia eXtensions
- SSE or Streaming SIMD Extensions, along with all its variants such as SSE2, SSE3, SSSE3, SSE4, SSE4.1, and SSE4.2
- POPCNT or Population Count
- AVX or Advanced Vector Extensions, along with AVX2
- AES or Advanced Encryption Standard
- CLMUL or Carry-less Multiplication
- FSGSBASE instructions for FS and GS segment registers
- RDRAND or Read Random
- FMA3 or Fused Multiply Add
- F16C or 16-bit floating point conversion instructions
- BMI or Bit Manipulation Instructions along with BMI2
- VT-x and VT-d or Virtualization extensions
- TXT or Text File extension
- TSX or Transactional Synchronization Extensions
- RDSEED or Read Random SEED
- ADCX or Add-Carry Instruction Extensions
- PREFETCHW or Prefetch Data into Caches in Anticipation of a Write
- CLFLUSHOPT or Flush Cache Line Optimized
- XSAVE or Save Processor Extended States
- SGX or Software Guard Extensions
- MPX or Memory Protection Extensions
Cache Memory Hierarchy
The cache memory of the Amber Lake processors is divided into L1, L2, and L3 cache, where the Level 1 cache is divided into two parts, one for the instructions called the L1I cache, and the other for data, called the L1D cache.
The Level 1 instruction and data caches both come with the following features:
- 32 KiB per core
- 8-way set associative
The Level L2 cache comes with the following features:
- 256 KiB per core
- 4-way set associative
The Level 3 cache comes with the following features:
- 2 MiB per core
- Up to 16-way set associative
The cores of the Amber lake processors are however named Whiskey Lake U and support a variety of arch-specific and arch-favorable compilers due to its specific architecture such as:
- ICC or Intel C Compiler
- GCC or GNU Compiler Collection
- LLVM or Low Level Virtual Machine and
- Visual Studio.
Amber Lake Y
Intel also released a very low-power line of CPUs on Amber Lake Y cores later on. These particular processors are mainly designed to be used in smaller mobile devices such as:
- Light notebooks
- Portable All-in-Ones
- Conference room
- 2-in-1 detachable systems
- Computer sticks
These processors are built on the more advanced 14 nm ++ process from Intel and support a slightly higher CPU clock rate.
The Amber Lake Y processors are also single-chip solutions, and there is a lightweight On-Package Interconnect (OPI) interface that helps in communicating among the separate dies.
This interface supports a 4 GT/s data transfer rate, which, in turn, increases the overall performance.
The common features of all of the Amber Lake Y processors are as follows:
- Dual-channel memory support for up to 16 GiB and up to DDR3L-1600 and LPDDR3-1866
- Dual core and four threads
- 10-12x PCIe
Additional Instruction Sets and Technology Support
Apart from the instruction sets mentioned above, the Amber Lake Y processors also support a couple of additional ISAs such as:
However, not all Amber Lake Y models support the AVX or AVX2 Instruction Set Architectures.
In addition to that, these specific processors also support a few other technologies such as:
- RAID or Redundant Array of Independent Disks
- AHCI or Advanced Host Controller Interface
- Smart Response
- High Definition Audio
- 6x USB 3.0 ports
- 6x USB 2.0 ports
- 4x Serial Advanced Technology Attachment or SATA III
- 6x I2C or Inter-Integrated Circuit
- 3x UART or Universal Asynchronous Receiver-Transmitter
- 1x SDXC or Secure Digital Extended Capacity
Typically, these specific processors support UHD Graphics 617 and UHD Graphics 615 (Gen 9.5 GT2) with the following features and abilities:
- Base frequency of 300 MHz
- Burst frequency ranging between 900 MHz and 1050 MHz
- Support offered for up to three independent displays.
The architectural design of these processors allows them to offer a significantly higher and better performance in comparison, when used in low-power mobile devices.