What is FPM DRAM (Fast Page Mode DRAM)? (Explained)

What is FPM DRAM (Fast Page Mode DRAM)?

The Fast Page Mode DRAM refers to the dynamic memory with a fast page access that offers a higher and faster performance with abbreviated address support in comparison to the standard Dynamic Random Access Memory (DRAM).

Technically, in an FPM DRAM, an address is determined uniquely by the column number only, not needing the line number, if the ensuing requested cell is in the same line as the preceding one.

KEY TAKEAWAYS

• Fast page mode DRAM supports fast page mode.
• It is faster and better than a standard DRAM.
• This specific type of memory module consumes less power.
• In this cost-effective technology, the controller keeps the Remote Access Services in a low state to prevent retransmission of row numbers.
• During a page cycle, the FPM DRAM does not need column address setup time, allowing faster access.

Understanding FPM DRAM (Fast Page Mode DRAM)

A DRAM memory offering support for burst technique and support is called Fast Page Mode Dynamic Random Access Memory.

These specific types of memory modules have the ability to access data on the same page with reduced latency.

An FPM DRAM does not need to send both rows and columns for each address like a standard DRAM.

It is an enhanced version of the Memory Page Mode, its predecessor, which is hardly used today.

The principle of operation of the FPM DRAM involves the progressive reading of memory cells and the processing of compact data structures of a couple of kilobytes. This reduces the access time by as much as 40% or more.

This is basically possible due to the fact that there is an internal buffer chip which holds the processed line.

This eliminates the need for accessing the matrix memory.

Ideally, when memory is accessed within the same address page or row, it needs only a single precharge for the first access.

All succeeding accesses to that specific page are then made quickly without needing any additional precharge cycle which eliminates the time penalty.

This is made possible by the controller of the FPM DRAM which keeps the Remote Access Services or RAS in a low state.

This helps in getting rid of the chances of the row numbers being retransmitted.

On the other hand, this is not possible in a regular DRAM because the RAS signal is deactivated after a data is read for preparing the chip for the following exchange cycle. This makes them slower than the FPM DRAM.

Working Principle

Ideally, the working principle of the FPM DRAM is founded on the hypothesis of a sequential data access.

This means that it is presumed that the data to be accessed in a memory array is organized in a series in the same row. Here, the page itself acts as the matrix row.

In this mode of access, there are multiple installations made for the column address when a row is selected and the RAS is retained.

These installations are usually gated by the Content Address Storage or CAS.

This approach needs only half of all the outputs to specify read and write data addresses and helps in the following:

• Selecting serial data in one line
• Eliminating the need to change the address
• Using only one or the same RAS signal
• Expediting block transfer

The operation happens in this specific way:

• The location of the first line is initiated by the memory cycle by using only half of the address bits.
• The other half is then used to access the column address of that particular data.

The reading or writing of data from or to the memory happens subsequently and for all following addressing, the next column is used without respecifying the row.

The two major benefits of this approach are:

• It reduces access times.
• It increases productivity.

Usually, the memory cycle time of an FPM DRAM is 50 nanoseconds. This allows accessing the memory at a frequency of 30 MHz, or 30 million times per second.

This is good enough for a memory bus with a clock rate ranging between 60 MHz and 66 MHz, which is typical for a Pentium processor.

When multiple cycles are needed for the memory access, it is usually done in a batch mode.

This means that every access does not need to specify the memory address because it is normally performed with reference to the ordered memory cells. If that does not happen, the added memory access data is ignored.

Usually, accessing memory in batch mode is shown by the formula 6-3-3-3, which means:

• Six clock cycles are required for the first memory access to specify the address fully.
• Three clock cycles are required for every three subsequent applications.

These clock cycles are usually in reference to the memory bus speed of the CPU. More often than not, a 60 MHz or 66 MHz clock frequency corresponds to the internal clock speed of the CPU of 120 MHz or 133 MHz, respectively.

Conclusion

FPM DRAM is a useful and cost-effective mode for applications where highest performance is not a priority but faster data access in memory is vital.

Though it is not as fast as the Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), it is still used in quite a few applications even today.