What is HyperTransport? (Explained)

What is HyperTransport?

HyperTransport, also referred to as HT sometimes, is the technology that represents a point to point link that offers high speed and low latency. It expedites the communication speed by 48 times than the current technologies.

Technically it is designed to be integrated into the CPU directly but in some cases it is also used as a high performance integrated I/O bus that has the ability to work with USB, PCI, PCI-X, Firewire and A/V links via the system.

KEY TAKEAWAYS

• HyperTransport is an AMD technology introduced first on April 2, 2001 with an initial signaling rate of 1.6 GHz on every pair of wire. The collective peak bandwidth of it is up to 12.8 GB/s.
• This integrated I/O bus is the open replacement of FSB and other legacy buses and bridges used in computers.
• Also codenamed as Lightning Data Transport, this high speed bus is used extensively today in computers, communication equipment, servers, embedded and many high-end networking systems.
• This specific I/O standard connects some general purpose processors directly with other parts and can operate at a much higher maximum frequency but at 500 MHz only in an FPGA.
• This specific bus comes in four versions such as 1.x, 2.0, 3.0, and 3.1 and their operating range varies from 200 MHz to 3.2 GHz with Double Data Rate support which allows faster data transfer.

Understanding HyperTransport Technology

Invented and released by AMD, the HyperTransport technology is designed to be used in computers, microprocessors and several embedded systems.

It can increase the speed of communication by 48 times than any other technologies due to its low latency.

Quite naturally, with the features and benefits offered, it has replaced the need for a Front Side Bus.

Managed and licensed by other contributors who form the HyperTransport Technology Consortium, this particular bus technology acts as a high speed point-to-point link.

The major contributors and members of the HT Consortium include:

• AMD
• Apple
• NVIDIA
• CISCO and many others.

This specific technology is packet-based. This means that it sends data in small packets that contain 32-bit words.

Apart from helping in communicating between different integrated and connected devices, this technology also helps significantly in power management.

HyperTransport technology is compliant with different power interface specs and advanced configurations and is specially designed. This helps it in several ways while operating which includes:

• Using low pin counts
• Offering low-latency responses
• Being transparent to the operating systems
• Making very little or no impact on the peripheral drivers
• Maintaining compatibility with the legacy computer bridges and buses
• Being extensible to the latest buses of systems network architecture and
• Providing radically more bandwidth.

Also known as Lightning Data Transport or LDT, this specific bus increases the system performance dramatically.

This is accomplished by it by facilitating parallel communication between the memory and other peripherals on-board.

It actually acts as a dedicated bus structure for the CPU and the memory to be in constant communication.

Unlike FSB or Front Side Bus and other buses that need to support all other components of the board, HT is designed to overcome that and therefore can perform at a great speed.

A separate link is utilized in order to handle the input and output operations of the Central Processing Unit of the computer. This basically allows the CPU to send data signals in parallel.

In comparison, on any other traditional bus, such operations cannot be performed at the same time.

The processors that are not built on the AMD 64 architecture have only the FSB as the external bus to connect the CPU to all other parts of the motherboard.

However, those that follows the AMD 64 architecture, has two such buses:

One of these is the HyperTransport bus that helps in communicating directly between the CPU and the other parts on the motherboard chipset and the other is the transport bus that transfers data between the CPU and the memory.

In the server systems, the HT bus allows connecting several processors as well.

HyperTransport Bus

HyperTransport bus is a high bandwidth state-of-art path that is highly scalable and is packet based. This point-to-point interconnect links several CPUs with one another, processor to I/O and peripheral controllers as well as processors to coprocessors.

This particular bus follows a highly optimized and high performing technology being designed on a board level architecture.

This Lightning Data Transport bus is typically designed to be a bidirectional serial or parallel bus.

Characteristically, this cutting edge technology uses the Low Voltage Differential Signaling or LVDS feature in its design which is not only very easy to implement but also enables it to deliver maximum bandwidth.

Used extensively in open architecture and embedded systems, this bus offers up to 51.2 GB/s bandwidth on an average for CPU to CPU or CPU to I/O connection.

Typically, this highly efficient chip-to-chip bus technology replaces the current multi-level and complex buses.

The design and features of these buses offers several benefits which include:

• Better frequency scalability and
• Low implementation cost.

The software used in these buses make them compatible with other well-known bus technologies such as:

• Peripheral Component Interconnect or PCI
• PCI-X and
• PCI Express or PCIe.

In short, it is the design of these buses that enables them to deliver increased data output but minimizes Electromagnetic Interference or EMI and signal crosstalk.

And, following the data packet protocol, the HT buses can do away with command, control and other sideband signals and at the same time support data paths of asymmetric and variable widths.

Available in four versions namely, 1.x, 2.0, 3.0, and 3.1 and with an operating range of 200 MHz to 3.2 GHz, this bus supports DDR or Double Data Rate.

This means that data can be sent both on the rising and falling edges of the clock signal which allows it to achieve a highest data rate of 6400 MT/s while operating at 3.2 GHz.

The frequency, year of release, maximum operating frequency, link width and aggregate bandwidth specifications for bi-directional, 16-bit unidirectional and 32-bit unidirectional data transfer respectively of different versions of HyperTransport bus are as follows:

• Version 1.0 – 2001, 800 MHz, 32-bit, 12.8 GB/s, 3.2 GB/s, and 6.4 GB/s
• Version 1.1 – 2002, 800 MHz, 32-bit, 12.8 GB/s, 3.2 GB/s, and 6.4 GB/s
• Version 2.0 – 2004, 1.4 GHz, 32-bit, 22.4 GB/s, 5.6 GB/s, and 11.2 GB/s
• Version 3.0 – 2006, 2.6 GHz, 32-bit, 41.6 GB/s, 10.4 GB/s, and 20.8 GB/s
• Version 3.1 – 2008, 3.2 GHz, 32-bit, 51.2 GB/s, 12.8 GB/s, and 25.6 GB/s.

The operating frequency is auto-negotiated with the Northbridge of the motherboard chipset while computing.

Who Created HyperTransport?

HT technology was created and developed by AMD and was launched on April 2, 2001.

Valuable contributions are also made by a few other major companies like NVIDIA, Apple, CISCO and others who also form the HyperTransport Consortium for its further development and proper management.

What Does HyperTransport Do?

HyperTransport technology increases the speed and performance of the overall system with more efficient data transfer and power management.

HT technology expedites a lot of different and specific computing tasks which include and are not limited to:

• 3D graphics and rendering
• x86 computing
• Media processing
• Security processing
• Application specific co-processing and acceleration and
• Data packet analysis in real time.

The better features and higher functionality of this technology perhaps have the largest range of applications and is adopted by the leaders in the industry for its highly efficient protocol and market-proven solidity.

It supports an auto-negotiated bit width of 2 to 32 bits in each link which helps it to operate at a much faster rate in comparison to most of the traditional bus standards when it comes to high-performance networking or computing.

When it comes to linking, it links different widths mixing them together in one particular system configuration to connect to the CPU and the peripheral device.

This allows adjusting the interconnect bandwidth appropriately between the CPU and the peripherals.

Add to that, HT also allows link splitting. This means that one 16-bit link can be split into two 8-bit links.

Depending on the version used, HyperTransport also allows post-cursor and optional precursor transmitter de-emphasis along with additional jumbling and receiver phase alignment.

It also facilitates power management because it abides by the specifications of Advanced Configuration and Power Interface or ACPI.

This means that when there are changes in the C state or in the processor sleep state it will also signal a change in the D state or the device state.

HT 3.0 also comes with additional functionalities that help in implementing a central power management controller for better power managing policies.

Is It Still Used Today?

Yes, HyperTransport technology is extensively and successfully used today in several high-end processors and systems.

Being a processor-native point-to-point link, HyperTransport is used in a large number of processors or CPU families of different manufacturers to serve a wide range of performance intensive applications.

Some of the most significant applications of this board-to-board, chassis-to-chassis and chip-to-chip high-performance interconnect and unique technology of AMD includes:

• Personal computers
• Servers
• Workstations
• Supercomputers
• Embedded systems
• Consumer as well as commercial applications
• Mission-critical projects
• Gaming systems and
• High-end network and communication equipment.

It is favored so much because right from its launch in April 2001, the HT Consortium has hard-pressed its limits to create newer and better revisions of the HT link.

One such is the HTX slot connector with the inclusion of High Node Count specifications and more.

This has made this specific technology offer higher performance with better features with better architectural reliability and flexibility.

Is HyperTransport Same as Multithreading?

No it is not. HyperTransport refers to the technology or the low latency bus that allows faster transport of data between the memory and the processor.

On the other hand, multithreading refers to a specific technique in which one particular set of code is used by many processors for execution at different stages.

Does Intel Use HyperTransport?

No, Intel does not use HyperTransport as such but it uses QuickPath Interconnect which is a competitor of HT with some similarities and differences. 

The similarities of the Intel QuickPath Interconnect with HyperTransport of AMD are:

• It also works with CPUs that come with memory controllers integrated in them
• It is also designed on the Double Data Rate technology and
• It reduces the overheads related to Front Side Bus architecture.

However, this path does have some specific overheads that are more than HyperTransport.

One of the most specific ones is that it needs 16 bits of overhead while sending 64 bits of data through it as opposed to 8 bits and 12 bits respectively for reads and writes in the case of HyperTransport.

As for the design aspects, the QuickPath architecture supports five different networking levels which are somewhat similar to the Open System Interconnection or OSI network layers. These are:

• The Physical Layer that involves the physical wiring as well as the data transmitters and receivers of the connections along with the lanes on each direction that are 20 bit wide
• The Link Layer that defines actual receiving and sending of data using 8 bits in 72-bit sections for Cyclic Redundancy Check or CRC error detection which means that a total of 80 bits data is sent in each direction through each of the lanes
• The Routing Layer that sends a chunk of 72-bit data to the link layer which consists of 64 bits data and 8 bit header where the former signifies the throughput and the latter signifies the message type and destination
• The Transport Layer that handles the data transmission errors and also makes a request for retransmission if there are any errors detected and
• The Protocol Layer that deals with the coherency of cache and determines how exactly a higher level program should access the data transfer mechanism in the interconnect.

The QuickPath Interconnect of Intel is designed to link several processors to the I/O controller as well as with each other.

The HyperTransport bus also does the same but in addition to that it also allows using it for connecting different add-on cards.

Apart from that, it also acts as a mechanism to transfer data between different switches and routers.

Conclusion

HyperTransport is a useful technology that allows better connection with the Central Processing Unit, memory and other parts of the motherboard.

It allows faster data transfer and also increases the overall performance of the computer system by offering much better performance in comparison to traditional buses.