What is Sandy Bridge? (Explained)

What is Sandy Bridge?

Sandy Bridge refers to the codename for the Intel processors typically belonging to the 2^nd generation Core i3, Core i5 and Core i7 processors.

Technically, these CPUs are typically built on 32 nm node technology and use an LGA 1155 type socket. They usually come with two, four, and six cores.

KEY TAKEAWAYS

• Sandy Bridge refers to the microprocessor architecture designed by Intel and released in early 2011 after the Nehalem CPU series.
• These processors belong to the 2^nd generation of the Intel Core family of processors and usually have 2, 4, or 6 cores.
• These CPUs support HyperThreading technology, which increases the performance level and speed of computing.
• The Sandy Bridge architecture consists of anywhere between one and two billion double-gate transistors.
• Sandy Bridge processors are available in Core i3, Core i5, and Core i7 variants with advanced video encoding and decoding features.

Understanding Sandy Bridge

Sandy Bridge of Intel is a microarchitecture of the processors of 2^nd generation and is a successor to Nehalem microarchitecture and released in early 2011.

It has a relatively larger die size of 32 nm and is built on ‘tock’ technology, but offers reasonably high performance.

These processors belong to different processor families of Intel having different cores and designed to serve specific purposes such as:

• Intel Celeron with 1 or 2 cores is designed as entry-level budget CPUs
• Intel Pentium with 2 cores is designed as budget CPUs
• Intel Core i3 with 2 cores that offer low-end performance
• Intel Core i5 with 2 or 4 cores that offer mid-range performance
• Intel Core i7 with 2, 4, or 6 cores is designed to offer high-end performance
• Intel Core i7EE with 4 or 6 cores is designed for offering enthusiasts/high-end performance

The Sandy Bridge processors are codenamed differently depending on their design and features such as:

• Sandy Bridge M, or SNB-M, designed to be used as mobile processors
• Sandy Bridge, or SNB, designed to be used as desktop processors
• Sandy Bridge E, or SNB-E, designed to be used for workstations and entry-level servers

These CPUs are compatible with different operating systems of Windows apart from Linux such as:

• Windows XP
• Windows Vista
• Windows 7

The Sandy Bridge also supports different arch-specific and arch-favorable compilers such as:

• LCC or Local C Compiler
• GCC or GNU Compiler Collection
• LLVM or Low Level Virtual Machine
• Visual Studio

Features:

There are lots of useful features and technologies included in the Sandy Bridge chip design that are upgrades from the previous chip designs.

Some of the notable features of Sandy Bridge CPUs are:

• Intel Turbo Boost 2.0
• 32 KB data and 32 KB instruction L1 cache
• 256 KB L2 cache per core
• Shared L3 cache including the processor graphics
• LGA 1155 socket type
• Cache line size of 64 bytes
• Enhanced 3-integer ALU
• Two vector ALU and two AGU in each core
• Two load/store operations for each CPU cycle for every memory channel
• Decoded micro-operation cache
• Optimized and enlarged branch predictor
• Support for AES encryption, transcendental mathematics, and SHA-1 hashing for improved performance
• 256-bit per cycle ring bus interconnect between the cores, cache, graphics, and System Agent Domain
• 256-bit Advanced Vector Extensions (AVX) instruction set with rich functionality, wider vectors, and new extensible syntax
• Up to 8 physical cores or 16 logical cores with HT
• Integrated Graphics and Memory Controller Hub (GMCH) which reduces memory latency
• An instruction pipeline of 14 to 19 stages
• Improved ROB to 168 entries
• Larger Scheduler buffer up to 54 entries

Architecture:

As for the architecture of the Sandy Bridge processors, it is completely redesigned as compared with its predecessors and comes with a brand new core design. Some of the notable architectural changes are:

• New client ring architecture
• New last level cache architecture with 4x bandwidth and multi-bank LLC or agent architecture
• New System Agent architecture with a new power management unit, Serial Voltage ID or SVID bus, and a completely re-architected Platform Environment Control Interface or PECI
• Chipset with Cougar Point
• Redesigned front-end with higher accuracy and a new µOP cache, branch prediction and single-level BTB
• New back-end with PRF instead of RRF renaming
• Improved instruction queue with 20 entries from 18 per thread
• Better macro-op fusion
• New design of Re-Order Buffer with increased functionality, new zeroing and onces idiom optimizations
• Better schedulers with larger buffer and execution units, rebalanced ports, 256-bit instead of 128-bit operations, and double FLOP/cycle
• 8-way L1 instruction cache instead of 4-way, 1 GiB page support with 4-entry/GiB page DTLB, double load throughput of 2 loads/cycle
• Loads and stores ability of AGUs with larger load and store buffer of 64 and 36 entries instead of 48 and 32 respectively
• Integrated graphics with a dropped QPI or Quick Path Interconnect controller and enhanced media capabilities and performance
• A 32 nm process from 45 nm
• A dedicated embedded DisplayPort instead of a PCIe interface with shared pins
• Integrated PCIe controller, memory controller, and Generic Debug eXternal Connection or GDXC

Memory Subsystem:

The memory subsystem of the Sandy Bridge processors is also reworked to offer a faster performance as follows:

• The L0 1,536 µOP cache is 8-way set associative supporting 32 sets of 6-µOP line size statically split between threads and each core and inclusive with L1 instruction cache.
• The L1 instruction and data cache is 32 KiB and 8-way set associative supporting 64 sets of 64 B line size and shared by two threads per core.
• The L1 data cache is 32 KiB and 8-way set associative supporting 64 sets of 64B line size and shared by two threads per core.
• The L1 data cache however uses four cycles to ensure faster load-to-use and five cycles for complex addresses and supports 16 B/cycle store bandwidth, 32 B/cycle load bandwidth and a write-back policy.
• The L2 cache is a 256-KiB unified, non-inclusive, 8-way set associative cache that supports 1024 sets, 64 B line size, 32 B/cycle bandwidth, 12 cycles for faster load-to-use, and a write-back policy.
• The shared L3 cache is up to 2 MiB for each core with 32 B/cycle at ring clock for read and write separately which is up to 16-way set associative and inclusive, supporting 64 B line size and a write-back policy with 26 to 31 cycle latency.
• The Dynamic Random Access memory or DRAM of the system has two channels with 8 B for each cycle at the memory clock and supports DDR3 memory of up to 1600 MHz.

Translation Lookaside Buffer:

The Translation Lookaside Buffer of the Sandy Bridge processors is dedicated and comprises a dedicated instruction L1 TLB or ITLB, a data cache TLB or DTLB, and a unified L2 TLB or STLB, and is designed to perform as follows:

• The ITLB can support 4 KiB page translations with 128 entries with its 4-way set associative dynamic partitioning and 2 MiB or 4 MiB fully associative page translations with 8 entries duplicated for every thread.
• The DTLB can support 4 KiB page translations with 64 entries and 2 MiB or 4 MiB page translations with 32 entries with its 4-way set associative fixed partitioning or 1 G page translations with 4 entries and fully associative fixed partitioning.
• The unified L2 TLB can support 4 KiB page translations with as many as 512 entries with 4-way set associative fixed partitioning and with 7 cycles ITLB miss and STLB hit.

Sandy Bridge vs Ivy Bridge

• The Sandy Bridge processors are slightly slower in performance, but, in comparison, the performance of the Ivy Bridge processors is slightly faster and higher.
• The Sandy Bridge processors consume a little more energy, but, when compared, the Ivy Bridge processors typically consume quite less power.
• The graphics performance of the Sandy Bridge processors is not as advanced as that of the Ivy Bridge processors.
• The Sandy Bridge processors belong to the 2^nd generation of Intel processor family but, in comparison, the Ivy Bridge processors belong to the 3^rd generation.
• The Sandy Bridge processors are good for playing older games but may struggle with the newer ones as opposed to the Ivy Bridge processors.
• The Sandy Bridge processors, released a year before the Ivy Bridge processors, are based on the ‘tock’ technology, but, in comparison, the Ivy Bridge processors are based on ‘tick’ technology.
• The technologies used in the Ivy Bridge processors are newer in comparison to those in the Sandy Bridge processors.
• The die size of the Sandy Bridge processors is a bit larger measuring 32 nm, while in comparison the die size of the Ivy Bridge processors is smaller, measuring 22 nm.
• The Sandy Bridge processors can be overclocked a little further than the Ivy Bridge processors, with good cooling, and operate within a speed ranging between 4.8 GHz and 5 GHz as opposed to the 4.5 GHz maximum of the latter.

Questions & Answers:

Conclusion

As is common with Intel, they always come up with better processor architectures and designs.

And Sandy Bridge is another turning point with improved features, a better design and functionalities.

As a result, its growing popularity is no coincidence, and people are happy using the Sandy Bridge processors even today.