Processors (CPU)

What is Zen Microarchitecture? (Explained)

January 8, 2023

In This Article

What is Zen Microarchitecture?

Zen refers to the codename of the microarchitecture of the family of AMD processors. Released in February 2017, it is found in the Ryzen processors used in desktop and mobile, Threadripper CPUs used in workstation and high end desktops, and EPYC for servers.

Over the years, different upgraded versions of Zen were released by AMD such as Zen+, which was released in April 2018, Zen 2, Zen 3, and Zen 4.

KEY TAKEAWAYS

Zen is the codename of the microprocessors manufactured by AMD, first released in February 2017.
There are different versions of it available such as Zen+, Zen 2 and so on, with diverse features.
The CPUs built on this particular architecture support different computing systems such as servers, workstations, high-end computing systems, notebooks and more.
The Zen microarchitecture is the successor to Puma and Excavator and comes with improved features.
The architecture design offers the right balance between power and performance, along with other aspects of the computing system.

Understanding Zen Microarchitecture

The Zen microarchitecture, which is the codename of the processors manufactured by AMD, supports different CPU lines such as:

Ryzen, for desktop and mobile devices
Threadripper, for workstation computers and High End Desktop or HEDT
EPYC, for server computers.

Picked by Michael Clark, the architecture is just right for all aspects of a processor including:

Die size
Transistor allocation
Power limits
CPU clock
Frequency restriction
New added instructions

Generations

There are different versions of it with different features which include the following:

14 nm FinFET fabrication process, which allows denser circuits on a small chip and higher performance and power efficiency
Infinity Fabric System Bus
Increased IPC or Instructions Per Cycle
Precision Boost
Extended Frequency Range (XFR) technology support

These features of Zen allow adjusting frequency and temperature dynamically for individual cores, helping in maximizing its performance.

The architecture includes CPU cores, RAM, PCIe, SATA, and others and increases the overall performance with its general design aspects, which include the following:

Write-back L1 cache rather than write-through, which allows higher bandwidth and lower latency
Simultaneous Multithreading (SMT) architecture instead of Clustered Multi-thread (CMT) design that allows for dual threads in each core
Four ALUs, two AGUs or load–store units and two floating-point units per core
Larger micro-operation cache
Six micro-ops per cycle for each SMT core
Faster L1 and L2 bandwidth
Higher L3 cache bandwidth
Clock gating
Larger load, store, and retire queues
Better branch prediction with a hashed perceptron system and an Indirect Target Array
Decoupled branch predictor from fetch stage
A dedicated stack engine to modify the stack pointer
Move elimination that decreases physical data movement and power consumption
RDSEED support
ADX support
SHA support
Page Table Entry (PTE) coalescing which allows combining 4 kiB page tables into 32 kiB page size
Pure Power monitoring sensors for more accuracy
Smart Prefetch

Add to that, the Zen microarchitecture also offers higher instruction support which includes:

SMAP or Supervisor Mode Access Prevention
SMEP or Supervisor Mode Execution Protection
XSAVEC or Save Processor Extended States with Compaction
XSAVES or Save Processor Extended States
XRSTORS or Restore Processor Extended States Supervisor
CLFLUSHOPT or Flush Cache Line Optimized
CLZERO

There are also a few other generations of Zen microarchitecture that came up in the following years. For example:

Zen+ is an upgrade of Zen and comes with improved features such as:

12 nm manufacturing process
Precision Boost 2
XFR 2
A slightly higher frequency and IPC.

Zen 2 is the successor to Zen+ and was released on July 7, 2019. It is designed with a much smaller 7 nm fabrication process and includes unique features such as hardware alleviation of the Specter vulnerability.

Zen 3 is the successor to Zen 2 and was released on November 5, 2020. It is also designed on a 7 nanometer fabrication process and supports four-way SMP with four cores sharing cache and RAM access.

Zen 4 is the successor to Zen 3 and was launched on September 27, 2022. It is designed on a 50 nm fabrication of TSMC.

Codenames

The Zen-based chips come with different codenames, such as:

Naples – They come with up to 32 cores and 64 threads and are intended for high-end server multiprocessors.
Whitehaven – They come with up to 16 cores and 32 threads and are intended for enthusiasts’ market processors.
Summit Ridge – They come with up to 8 cores and 16 threads and are intended for mainstream to high-end desktops.
Raven Ridge – They come with up to 4 cores and 8 threads and are intended for mobile processors with a Vega GPU.
Dali – They come with up to 2 cores and 4 threads and are intended for budget mobile processors with a Vega GPU.
Snowy Owl – They come with up to 16 cores and 32 threads and are intended for embedded edge processors.
Great Horned Owl – They come with up to 4 cores and 8 threads and are intended for embedded processors with a Vega GPU.
Banded Kestrel – They come with up to 2 cores and 4 threads and are intended for low-power and cost-sensitive embedded processors with a Vega GPU.

The AMD Zen-based processors come in different brand names as well, such as:

Quad-core Ryzen 3 processors, designed to provide entry level performance with unlocked multipliers and AVX2, SMT, XFR, and ECC support.
Quad-core and hexa-core Ryzen 5 processors, designed to provide mid-range performance with unlocked multipliers and AVX2, SMT, XFR, and ECC support.
Octa-core Ryzen 7 processors, designed to provide high-end performance with unlocked multipliers and AVX2, SMT, XFR, and ECC support.
Ryzen 9 processors with 12 to 16 cores, designed to provide high-end performance with unlocked multipliers and AVX2, SMT, XFR, and ECC support.
Ryzen Threadripper processors for enthusiasts and workstation computers with 8 to 16 cores that provide high-end performance with unlocked multipliers and AVX2, SMT, XFR, and ECC support.
Extreme Performance Yield Computing (EPYC) processors for server computers that provide high-end performance with 8 to 32 cores and with AVX2, SMT, MP and ECC support and those for embedded/edge server systems with AVX2 and ECC support.

There are also some Ryzen processors based on the Zen architecture that are designed to be used as embedded APUs with four cores and AVX2, IGP, and ECC support.

Compiler and OS Support

The Zen microarchitecture supports only the Windows 10 operating system and initial support to 4.10 kernel and full support to 4.15 kernel of Linux OS.

As for the compilers, the architecture supports the following:

AOCC or AMD Optimizing C/C++ Compiler
GCC or GNU Compiler Collection
LLVM or Low Level Virtual Machine

It also supports Visual Studio.

Cache

The parity-protected L0 µOP cache comes with the following features:

2,048 µOps
8-way set associative
32-sets
8-µOP line size

The parity-protected Level 1 instruction cache that is shared by two threads in each core comes with the following features:

64 KiB
4-way set associative
256-sets
64 B line size

The Level 1 data cache comes with the following features:

32 KiB
8-way set associative
64-sets
64 B line size
Write-back feature
4 to 5 cycles of latency for instructions
7 to 8 cycles of latency for FP
SEC-DED ECC

The Level 2 cache comes with the following features:

512 KiB
8-way set associative
1,024-sets
64 B line size
Write-back feature
L1 inclusive
17 cycles of latency only in Summit Ridge and 12 cycles in all others
DEC-TED ECC

The Level 3 cache comes with the following features:

Victim cache
8 MiB/CCX shared across all cores in Summit Ridge and Naples
4 MiB/CCX shared across all cores in Raven Ridge
16-way set associative
8,192-sets
64 B line size
40 cycles of latency
DEC-TED ECC

As for the system’s Dynamic Random Access Memory or DRAM, the features include the following:

Two channels on each die
Up to PC4-21300U, DDR4-2666 UDIMM and ECC support are available in Summit Ridge
Up to PC4-23466U, DDR4-2933 UDIMM and ECC support are available in PRO models of Raven Ridge
Up to PC4-21300L, DDR4-2666 RDIMM/LRDIMM and ECC support for Naples
x4 DRAM device failure correction
x8 SEC-DED ECC
Data positioning
Patrol and Demand scrubbing

Translation Lookaside Buffer

The Zen microarchitecture comes with a TLB for instruction cache called the ITLB and one for data cache called the DTLB with different features.

In the ITLB, there are:

8 entry L0 TLB of all page sizes
64 entry L1 TLB of all page sizes
512 entry L2 TLB with no 1G pages
Parity protection

In the DTLB, there are:

64 entry L1 TLB of all page sizes
1,532-entry L2 TLB with no 1G pages
Parity protection

Clocks

It supports different clock domains such as:

UClk or UMC Clock – This Unified Memory Controller clock operates at a frequency identical to the frequency of the memory clock.
LClk or Link Clock – This is the frequency at which the I/O Hub Controller interacts with the chip.
FClk or Fabric Clock – This refers to the clock frequency at which the data fabric operates, and it is also the same as the frequency of the memory clock.
MemClk or Memory Clock – This refers to the internal and external memory clocks.
CClk or Core Clock – This clock indicates the frequency at which the cores of the CPU and the caches operate. Ideally, this is the advertised frequency.

Security

There are several security features included in the Zen architecture such as:

There is a firmware residing externally on an SPI ROM, or Serial Peripheral Interface Read Only Memory, usually in the secure and dedicated processor that runs a secured kernel. It ensures secure management and key generation, along with hardware-validated boots, during different cryptographic operations.
Secure Memory Encryption or SME allows complete hardware memory encryption to prevent any physical attacks using only a single key. It also supports TSME, or Transparent SME, in the server models as well as in the workstation-class PRO processors.
Secure Encrypted Virtualization or SEV is a much more sophisticated version of SME that allows using individual keys for each hypervisor and each VM, a container, or a bunch of VMs. It encrypts the hypervisor memory and isolates it cryptographically from the guest machine.

Sockets

All mainstream Zen-based consumer processors use the AM4 Socket from AMD with a unified infrastructure.

However, the connectivity options offered may differ according to the processor and chipset type.

And, as for the Threadripper processors, they typically use the Socket TR4, or sTR4, or simply TR4.

Advantages

Smaller chip size that allows less power consumption
Increased performance by scaling frequency and voltage dynamically
Higher DDR4 memory support to up to eight channels with Error Correction Code (ECC) support
Clock gating which reduces power consumption and heat generation
Improved security and virtualization support with Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) from AMD
Better connectivity support

Conclusion

Also referred to as Family 17h, Zen is the successor to both Puma and Excavator and offers a perfect balance between power and performance.

It supports the entire range of computer systems available, right from the regular computing machines to the server computers and the fanless notebooks to the HEDTs.