CISC (Complex Instruction Set Computer) Explained

What is CISC (Complex Instruction Set Computer)

What is CISC (Complex Instruction Set Computer)?

Complex Instruction Set Computer, or CISC refers to the standard of computers designed to support up to two hundred instructions. Basically, it refers to the classification of a specific design of microprocessor.

Technically, the CISC structure consists of a large number of personal computer instructions including very easy, technical, and intricate ones designed on ‘more than one instruction per cycle execution’ principle.

It can carry out several tasks by using very little code.


  • Complex Instruction Set Computer is designed on a completely different spectrum to carry out several instructions in one execution cycle.
  • CISC is considered to be the predecessor of the Reduced Instruction Set Computer design and the instructions in it occupy more than one memory word.
  • There are different complicated instructions and addressing modes in CISC instructions which makes their decoding a bit complicated.
  • Despite the complexities in the instructions, the size of the program is smaller, which enables the CISC instructions to operate directly on the memory operands.
  • The primary goal of CISC is to support one machine instruction for every statement written in a high-level language.

Understanding (CISC) Complex Instruction Set Computer

What is CISC (Complex Instruction Set Computer)

In simple words, CISC refers to the approach which completes an entire operation in just a few lines using the assembly language code.

CISC uses instruction formats of variable length. For example, instructions that need register operands to take two bytes only.

However, those specific instructions that need two memory addresses may take up to 5 bytes for a complete code.

Therefore, varying lengths of encoding require a variable number of clock cycles.

There are a few added addressing modes in CISC such as:

  • Auto increment mode – In this mode the register content is the effective address of the operand. When this is accessed it is incremented automatically to the point of the memory location of the following operand.
  • Auto decrement mode – In this mode the effective memory operand address is the same as above but the content is decremented and is then used as the effective address of the operand.
  • Relative mode – In this mode, a constant is added to the substance of the general purpose register to get the effective address. Used to refer to a wider range of areas in the memory, the program counter is used in place of the general purpose register in this mode.

With its useful design, CISC offers some specific benefits which include:

  • Smaller codes allow completing several low-level tasks in a single instruction
  • Reduced work of the compiler since high-level language statement does not need to be changed into assembly language
  • Less RAM or Random Access Memory required due to shorter code length and
  • Direct access to memory locations by the instructions.

However, the CISC architecture does not allow easy instruction pipelining and the complexity of the instructions makes them a bit less efficient due to the large number of clock cycles required to carry out an instruction.

What is the Architecture of CISC?

The CISC architecture helps in using only one machine instruction for one statement. The architecture allows complex decoding of the instructions without needing several general purpose registers for that.

This is typically facilitated by the CISC processor which can manipulate the operands in the memory directly.

The architecture also allows the processor of the computer to perform a specific task using as few codes of the assembly language as possible.

Apart from that, the CISC architecture does not need loading data to the register from the memory in order to function.

This is because it can access and use the data directly in the memory for the specific operations.

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The architectural attributes of CISC result in a more complex instruction set with micro commands.

This increases the execution times of the instructions but the accumulated apps occupy less memory space.

However, the architecture supports applications written in assembly language and enables faster operations.

What Are the CISC Architecture Characteristics?

Some of the most significant features or characteristics of the CISC architecture include larger and complex instructions that need more complex decoding. Usually, these instructions take more than one cycle to be executed.

In addition to that, there are also a few specific features of CISC that facilitates its functioning such as:

  • Variable and large size and number of instructions typically ranging between 100 and 250
  • Infrequent uses of those instructions that carry out specialized tasks
  • A large number of addressing modes typically ranging between 5 and 20
  • A large number of commands
  • Specialized and complex commands
  • Lower clock frequency of the CPU
  • Ability to perform multiple low-level operations such as fetch, arithmetic operations and saving to memory in one single instruction
  • Micro programmable control unit
  • Complex instruction decoding
  • More data types and
  • Need for general purpose registers to perform the operations and store the results in the memory.

All these features make CISC quite useful for low-end applications.

How Do CISC Processors Work?

The CISC processors work on a single instruction that does everything from loading the values from the memory, evaluating them and storing the results of the operation back in the memory.

This minimizes the number of instructions required for each program but it increases the number of CPI or Cycles Per Instruction.

There is an entire set of special-function circuits that handles multiple instructions of variable sizes. Ideally, the working process of these processors is as follows:

  • Values are loaded with direct access to the memory
  • Instructions are carried out quickly by using complicated addressing modes for interacting with the memory
  • Carrying out arithmetic and logical operations for both the register operands and the memory
  • Hiding implementation programs from the machine level programs during operations
  • Using clean abstraction provided by the Instruction Set Architecture between the program and its execution and
  • Using condition codes and stack for process arguments and returns addresses.

Ideally, the working process of the CISC processors emphasizes more on the efficient use of Random Access Memory and the hardware rather than software, which makes them different from the RISC processors.

What is an Example of CISC?

Some of the best examples of CISC include simple microcontrollers and complex mainframe computers where the load and store operations of the memory are not distinct from the arithmetic instructions.

There are also a few specific processors that are built on the CISC architecture and are used in quite a few different computers such as VAX and System/360 computers of IBM.

There are also a few AMD and several generations of Intel x86 processors that are built on this architecture. Some of the most prominent examples of processors based on CISC architecture are:

  • IBM 370/168 – This 32-bit processor was introduced in 1970 with a CISC design that also included as many as four floating point registers of 64 bits.
  • VAX 11/780 – This is another 32-bit processor released by Digital Equipment Corporation based on the CISC design that supports a large number of machine instructions and different addressing modes.
  • Intel 80486 – This CISC processor was released in the year 1989 which could use instructions of variable length ranging from 1 to 11 with as many as 253 instructions.

A few other specific microprocessors that are built on the CISC Instruction Set Architecture include:

  • The DEC VAX
  • Motorola 68000 (68K)
  • PDP-11 and
  • Intel 8051.

As for the operations, an example of CISC would be an ADD instruction that uses index addressing for specifying an operand in the memory and for direct addressing of another operand.

Ideally, the instruction would use a different location altogether to store the result.

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This means that the ADD instruction would use as many as three different memory references to get completed.

Does CISC Use Pipelining?

Yes, technically, CISC uses pipelining but it is quite complex and is done entirely at a different level.

First, the complex instructions need to be broken down into simpler and smaller parts before these are pipelined.

However, in reality, these instructions are actually translated into a series of internal RISC instructions and these are then pipelined.

Ideally, in the CISC architecture, the instructions contained are a mixture of simpler ones that take shorter time and complicated ones that take longer time to get executed.

Therefore, there is a high chance of hazards being created in the pipeline that may result in several issues and affect the smooth operation of the pipelining.

In fact, it is mainly due to the complexity of the CISC instruction that makes them harder, if not unsuitable, and less beneficial to pipelining as compared to RISC.

Also, the varied length of the CISC instructions as opposed to the RISC instructions makes it difficult to fetch them all in one single operation.

That is the main reason that the majority of the CISC processors available these days are typically pipelined in out-of-order superscalar designs.

Does CISC Have Fixed Length?

Technically, no, and ideally, the length of CISC instructions of x86 in particular may be anywhere between 1 and 15 bytes. Considering the override bytes and the multiple instruction prefixes especially, exactly how far the length of the instructions could go is really not known.

In the cases of redundant repetitions of a few specific types of prefixes, there can be no limit at all.

Ideally, to a large extent, CISC is considered to be a design philosophy rather than architecture and therefore there is nothing as such called the ‘length’ of the instructions.

Therefore, theoretically it can be said that the instruction length in CISC may be infinite.

This is due to the reason that the prefixes can be repetitive. And, this particular aspect makes things complicated for the instruction decoder.

However, in practice, the instruction length has been limited to 15 bytes by the x86-64 AMD processors.

If it exceeds this limit then there is an error signal displayed by the instruction decoder stating that it has given up.

On the other hand, Intel started to limit the instructions up to 10 bytes in and from their 80286 and 15 bytes in their later ISA versions.

Why Does Intel Still Use CISC?

The main reason for Intel to continue using CISC is to blur the boundary that separates it from RISC and make it both hardware and software compatible.

It also offers speed enhancement than RISC. And, it is certainly and entirely not related to backward compatibility.

Considering the caches, CISC is also much better to use than RISC. If the same size of cache is used in both these architectures then that in CISC will have a much more effect in the operation.

This is primarily due to two specific reasons such as:

  • The high density code provided by the CISC architecture and
  • It is easy in terms of compiler implementation.

These reasons are quite strong enough to stick with CISC. It is also sensible because moving to RISC now, when the boundaries between RISC and CISC are almost eliminated, will be a grave mistake.

Moreover, there are a few specific sets of tradeoffs represented by the RISC architecture.

Considering the present realities and usability, these tradeoffs may cause significant issues that will be far more difficult and costlier to fix.

However, industry experts think that Intel viewed it in a different way and backed their intent with two-fold reasons. These are:

  • To lower the number of cycles required to carry out an instruction and
  • To enhance the clock speed.

The CISC architecture allowed them to easily hard-code the logic instead of micro-coding for every instruction.

This further helped in encoding the instructions in a much simpler way possible which helped in reducing the chip area because it did not need to be dedicated for decoding instructions.

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In fact, this was simply a waste of space that did not actually help in any way in getting the job done.

By sticking to the CISC architecture, Intel has been able to do away with all these issues to a large extent successfully.

What is the Need for CISC Architecture?

The most basic need for the CISC architecture is to use one machine instruction for multiple low-level operations and for every statement written in a high-level language and to perform different addressing modes or multi-step operations.

The architecture allows doing all these in several clock cycles.

In addition to that, the other specific needs for CISC are as follows:

  • It will make instruction encoding much simpler and relatively half the size of a typical RISC design
  • It will not need to use higher memory bandwidth to fetch the instruction and
  • It will not need a larger cache to accomplish the expected hit rate.

Therefore, as said earlier, moving from CISC to RISC today will be a big mistake and there are several reasons for it, apart from the above.

  • First and foremost, the speed of carrying out an individual instruction will not have any dramatic effect or difference due to the migration from CISC to RISC. This is because the speed of operation today largely depends on caching and the CPU speeds have also increased significantly so much that it is limited to power consumption almost entirely.
  • Second, there is also no difference in the number of cycles required to carry out an average instruction between both these architectures. This is because hard coding of instructions is no more exclusive to the RISC design and therefore can be implemented in CISC design as well.
  • Thirdly, due to the substantial change in the instruction decoding process, though not simplified, the number of transistors required for it does not really count anymore. This is because the instruction decoder is pretty small to use at least three of them in an x86 core which allows using less than 1% of the total transistors to execute an instruction by a modern processor.

So, there is nothing that will make things simpler which is why CISC is still needed today since there is a technical parity between RISC and CISC.

Where is CISC Architecture Used?

The microcontrollers and microprocessors that were first introduced used the CISC architecture. In addition to that, it is also used in low-end and real-time applications, such as home automation devices, security systems, and more.

When it comes to processors, CISC processors are used in:

It is also used in enterprise servers. This is because these CPUs can process more complex instructions such as loading two values from the memory and adding them as well as storing the results back in it, all in one instruction.

Is CISC Hardware or Software?

CISC typically is more focused on hardware design as opposed to RISC which is more of a software design. Since CISC is a hardware design, it is more difficult and needs a considerable investment.


A Complex Instruction Set Computer may be complex and difficult to improve but is quite useful in carrying out multiple operations by using one machine instruction.

Over the years, with advanced resources and development in technology, major roadblocks are removed to blur the boundary existing between CISC and RISC.

About Dominic Chooper

AvatarDominic Chooper, an alumnus of Texas Tech University (TTU), possesses a profound expertise in the realm of computer hardware. Since his early childhood, Dominic has been singularly passionate about delving deep into the intricate details and inner workings of various computer systems. His journey in this field is marked by over 12 years of dedicated experience, which includes specialized skills in writing comprehensive reviews, conducting thorough testing of computer components, and engaging in extensive research related to computer technology. Despite his professional engagement with technology, Dominic maintains a distinctive disinterest in social media platforms, preferring to focus his energies on his primary passion of understanding and exploring the complexities of computer hardware.

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Dominic Chooper
Dominic Chooper, an alumnus of Texas Tech University (TTU), possesses a profound expertise in the realm of computer hardware. Since his early childhood, Dominic has been singularly passionate about delving deep into the intricate details and inner workings of various computer systems. His journey in this field is marked by over 12 years of dedicated experience, which includes specialized skills in writing comprehensive reviews, conducting thorough testing of computer components, and engaging in extensive research related to computer technology. Despite his professional engagement with technology, Dominic maintains a distinctive disinterest in social media platforms, preferring to focus his energies on his primary passion of understanding and exploring the complexities of computer hardware.
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