What is Silvermont Processor? (Explained)

What is Silvermont Processor?

The Silvermont processors refer to the codename of the 22 nm microarchitecture of Intel and belong to the system on chips from the Atom family. Technically, this is an architecture that supports low-power Atom, Pentium and Celeron branded processors.

The Silvermont processors come with 2 to 8 cores, a 12 to 14 stage pipeline, several instruction sets and an integrated HD graphics processor that itself supports a lot of different technologies and operates at a reasonably high frequency.

KEY TAKEAWAYS

  • Silvermont is the codename of the system on a chip designed by Intel and is intended to offer an increased and faster performance while consuming low power.
  • The 22 nm manufacturing process as well as the Tri-Gate transistors are tuned for system-on-a-chip design to use in mobile devices such as phones and tablets as well as in Ultrabooks.
  • A lot of new instruction sets are supported by these specific processors in comparison to the architecture of the previous generations.
  • Silvermont primarily is the basis of four specific System on a Chip families, which include Merrifield and Moorefield, Bay Trail, Avoton, and Rangeley.
  • The 12 to 14 stages pipeline supported by this particular processor architecture helps significantly in the instruction fetching, decoding, and branch prediction processes.

Understanding Silvermont Processor

What is Silvermont Processor

Silvermont is the codename of the microarchitecture used to design low-power processors of different brands, such as Atom, Celeron and Pentium, and to be used in the System on a Chip (SoC) made by Intel.

This successor to Saltwell and Bonnell is specially designed for using in smaller devices such as:

  • Smartphones
  • Tablets
  • Embedded system
  • Consumer electronics

Silvermont basically forms the foundation for a total of four SoC families, such as:

  • Merrifield and Moorefield
  • Bay Trail
  • Avoton
  • Rangeley

However, here is the further breakup of these families, with some additional information.

  • The Merrifield platform uses Tangier cores that are designed for use in smartphones.
  • The Moorefield platform uses Anniedale cores that are designed for use in high-end smartphones.
  • The Bay Trail platform uses cores by the same name that are designed to be used in smaller devices such as tablets, netbooks, nettops, and other hybrid devices, as well as embedded and automotive systems.
  • The Edisonville platform uses Avoton cores that are designed for use in the microservers as well as in the storage devices.
  • The Edisonville platform also uses Rangeley cores that are designed to be used in embedded networks and communication infrastructure.

Features

There are a slew of innovative features included in these processors that also help in improving the power efficiency and performance level of them in comparison to their predecessors.

Some of these useful features are:

  • Out-of-Order Execution (OoOE) – This feature helps in executing the instructions as soon as the data is available for processing, instead of following the precise order laid down by the software program.
  • Branch processing – This feature happens to be more efficient than before, offering more accurate results and branch predictors. This allows for faster recovery from pipeline collisions or crashes.
  • FPU latency – This is perhaps one of the most significant improvements in this particular architecture that offers the biggest boost in its performance and throughput.
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All these features allow executing more instructions in quick time, which almost doubles the eventual throughput, because it does not have to wait for the earlier instructions to be completed to start executing the new one.

Instructions

There are lots of features in Silvermont that are apparently borrowed from Westmere, but if you look at the instructions in particular, there are lots of additional instructions included in the design.

Some of these instructions are:

  • AES-NI or Advanced Encryption Standard New Instructions that allows for hardware-level encryption or decryption along with several other hardware-accelerated AES operations
  • Secure Key that allows for random number generation
  • SSE 4.1 or Streaming SIMD Extensions Version 4.1
  • SSE 4.2 or Streaming SIMD Extensions Version 4.2
  • MOVBE or Move Data After Swapping Bytes that helps in carrying out the Move Big-Endian instruction
  • CRC32 or Cyclic Redundancy Check 32 that allows for hardware-accelerated cyclic redundancy check
  • POPCNT or hardware-accelerated Population Count
  • CLMUL or hardware-accelerated Carry-less Multiplication
  • RDRAND or Read Random which is a Secure Key Technology extension
  • PREFETCHW or or Prefetch Data into Caches in Anticipation of a Write which refers to prefetch data into caches that hints at an anticipated write in the future.

Memory hierarchy

The memory distribution in the Silvermont processors is also quite significant and worth noting.

The features of the Level 1 instruction cache are as follows:

  • 8-way set associative
  • 32 KiB instructions per core
  • 64 B line size

The features of the Level 1 data cache are as follows:

  • 6-way set associative
  • 24 KiB data per core
  • 64 B line size

The features of the Level 2 cache are as follows:

  • 16-way set associative
  • 1 MiB per two cores
  • 64 B line size with 32 B per cycle
  • 14 cycle latency

There is no Level 3 cache, however.

The details of the Random Access Memory supported by the Silvermont processors are as follows:

  • Maximum support of 1 GiB, 2 GiB, and 4 GiB
  • Dual 32-bit channel support with 1 or 2 ranks in each channel

Pipeline

The Silvermont processors also support a pipeline using a dual-issue design like its predecessor, the Saltwell, but it is 2 stages shorter and the branch misprediction penalty is also 3 cycles lower.

The general features of the Silvermont pipeline are:

As said earlier, the Silvermont microarchitecture supports OoO execution, which enhances the speed of instruction execution and lowers latency.

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Ideally, the design of this microarchitecture allows the pipeline for decoding and issuing two instructions and dispatching five operations in one single cycle.

Stages of the Pipeline

The different stages of the pipeline are used to carry out different processes as follows:

Instruction Fetch

As it was in the earlier microarchitectures, the instruction fetch process takes up the initial three stages of the pipeline.

However, in the Silvermont architecture, the instruction fetching and ranch prediction processes are much more aggressive due to the introduction of the Out-of-Order Execution.

This means that the instructions in the Silvermont architecture will not get stalled and will not clog the whole pipeline, as they did in the case of its predecessor, the Saltwell.

Instruction Decode

Once again, in the earlier generations of microarchitectures, instruction decoding was a bit of a problem.

This is because approximately 5% of instructions are split up into micro-ops by the common software code.

On the other hand, in Silvermont, this is even brought down to as little as 1 or 2%. It is due to this reduction in the amount of micro-ops it translates into the performance of the processors directly.

The level of performance is significantly increased due to the fact that not less than 3 to 4 additional cycles are eliminated from the overhead.

There is also a second branch predictor in Silvermont, which helps it in making more precise predictions according to the information that is not known earlier.

It can be the information regarding the target address from the register or the memory or any other. This helps to override the generic predictor.

There is no need to worry about branch misprediction because the cost of it is also reduced in the Silvermont processors.

This is due to the fact that in this architecture, the branch misprediction penalties are lowered by 3 stages, down to 10 cycles, as opposed to 13 cycles in its predecessor, Saltwell.

Branch Prediction

There are two branch predictors in Silvermont that help in the branch prediction process as follows:

  • One that controls and helps with the instruction fetching process and
  • The other that can override the first instruction after gathering additional information during the process of decoding.

Here, the second predictor is responsible for controlling the process of speculative instruction issuance.

As for the first predictor, the Silvermont architecture allows for the use of the Branch Target Buffer or BTB in order to figure out the following fetch address, which may even include a 4-entry Return Stack Buffer.

This helps significantly in handling the calls and returns.

Integrated Graphics Processor

Some of the Silvermont processors come with an integrated graphics processor in them. For example, the Silvermont processors that support an HD Graphics (4 EU) include brand names as follows:

  • Pentium and Celeron desktop processors with base and boost GPU frequencies ranging between 688 MHz and 896 MHz
  • Atom embedded or automotive processors with base and boost GPU frequencies ranging between 400 MHz and 792 MHz
  • Atom mobile processors with base and boost GPU frequencies ranging between 311 MHz and 896 MHz
  • Atom tablet processors with base and boost GPU frequencies ranging between 311 MHz and 833 MHz
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The smartphone processors also come with an integrated graphics processing chip that supports an operational frequency ranging between 400 MHz and 64 MHz, depending on the model of CPU.

Depending on the version and type of the HD Graphics Processing Unit, they offer different types of support, such as:

  • DirectX 11
  • OpenGL 4.0
  • OpenCL 1.1
  • OpenGL 4.0
  • OpenGL ES 3.1

General Information

To round up every technical and physical aspect of the Silvermont processors and the architecture, here is the complete rundown of it with some general facts and information summarized for you:

  • The architecture supports caches with low latency and high bandwidth.
  • It also supports Out-of-Order memory transactions.
  • It was launched in 2013.
  • It is built on the 22 nm technology node, which is based on 3D Tri-Gate transistors.
  • It supports x86 System on a Chip architecture.
  • It supports x86-32 and x86-64 Instruction Set Architecture or ISA, along with several instruction extensions, including VT-x.
  • The number of cores supported by this architecture ranges between 2 and 8.
  • The processors are available under different brand names, such as Atom, Celeron, and Pentium.
  • The predecessors of this architecture are Bonnell and Saltwell.
  • The successors to this architecture are Airmont and Goldmont.
  • The Thermal Design Power or TDP of the Silvermont desktop processors is usually within 10 watts.
  • The TDP of the Silvermont mobile processors ranges between 4.5 watts and 7.5 watts.
  • The TDP of the server and communications processors is typically 20 watts.

Conclusion

The Silvermont architecture is suitable for designing processors to be used in different small devices, such as smartphones and tablets.

However, the features and functionalities of these processors, along with their architectural support, allow them to be used in server and desktop computers as well.

About Dominic Cooper

Dominic CooperDominic Cooper, a TTU graduate is a computer hardware expert. His only passion is to find out the nitty gritty of all computers. He loves to cook when he is not busy with writing, computer testing and research. He is not very fond of social media. Follow Him at Linkedin